platform/x86: intel/pmc/core: Add Meteor Lake support to pmc core driver

Add Meteor Lake client and mobile support to pmc core driver. This patch
adds legacy support.

Cc: David E Box <david.e.box@linux.intel.com>
Suggested-by: David E Box <david.e.box@linux.intel.com>
Reviewed-by: "David E. Box" <david.e.box@linux.intel.com>
Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Signed-off-by: Gayatri Kammela <gayatri.kammela@linux.intel.com>
Signed-off-by: "David E. Box" <david.e.box@linux.intel.com>
Link: https://lore.kernel.org/r/20221114183257.2067662-9-gayatri.kammela@linux.intel.com
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/drivers/platform/x86/intel/pmc/Makefile b/drivers/platform/x86/intel/pmc/Makefile
index 0135918ea718060a8fa834a4f918bb1481166971..f96bc2e19503423d66efeeeee4f61b849f3fe038 100644 (file)
--- a/drivers/platform/x86/intel/pmc/Makefile
+++ b/drivers/platform/x86/intel/pmc/Makefile
@@ -4,7 +4,7 @@
 #
 
 intel_pmc_core-y                       := core.o spt.o cnp.o icl.o tgl.o \
-                                          adl.o
+                                          adl.o mtl.o
 obj-$(CONFIG_INTEL_PMC_CORE)           += intel_pmc_core.o
 intel_pmc_core_pltdrv-y                        := pltdrv.o
 obj-$(CONFIG_INTEL_PMC_CORE)           += intel_pmc_core_pltdrv.o

diff --git a/drivers/platform/x86/intel/pmc/core.c b/drivers/platform/x86/intel/pmc/core.c
index 14dfeac735215f20933a23cb4ed7a5720d7edf57..f1d802f6ec3f9172605b385e86dafbfbd2de09b8 100644 (file)
--- a/drivers/platform/x86/intel/pmc/core.c
+++ b/drivers/platform/x86/intel/pmc/core.c
@@ -901,7 +901,11 @@ static void pmc_core_get_low_power_modes(struct platform_device *pdev)
                return;
 
        lpm_en = pmc_core_reg_read(pmcdev, pmcdev->map->lpm_en_offset);
-       pmcdev->num_lpm_modes = hweight32(lpm_en);
+       /* For MTL, BIT 31 is not an lpm mode but a enable bit.
+        * Lower byte is enough to cover the number of lpm modes for all
+        * platforms and hence mask the upper 3 bytes.
+        */
+       pmcdev->num_lpm_modes = hweight32(lpm_en & 0xFF);
 
        /* Read 32 bit LPM_PRI register */
        lpm_pri = pmc_core_reg_read(pmcdev, pmcdev->map->lpm_priority_offset);
@@ -1024,6 +1028,7 @@ static const struct x86_cpu_id intel_pmc_core_ids[] = {
        X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_P,        tgl_core_init),
        X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE,          adl_core_init),
        X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_S,        adl_core_init),
+       X86_MATCH_INTEL_FAM6_MODEL(METEORLAKE,          mtl_core_init),
        {}
 };
 

diff --git a/drivers/platform/x86/intel/pmc/core.h b/drivers/platform/x86/intel/pmc/core.h
index 129c0c98f1a6fe20d3c614a290977eb9b939983a..810204d758ab3a6b33d53092b87739ca5db2ac5a 100644 (file)
--- a/drivers/platform/x86/intel/pmc/core.h
+++ b/drivers/platform/x86/intel/pmc/core.h
@@ -238,6 +238,16 @@ enum ppfear_regs {
 #define ADL_LPM_STATUS_LATCH_EN_OFFSET         0x1704
 #define ADL_LPM_LIVE_STATUS_OFFSET             0x1764
 
+/* Meteor Lake Power Management Controller register offsets */
+#define MTL_LPM_EN_OFFSET                      0x1798
+#define MTL_LPM_RESIDENCY_OFFSET               0x17A0
+
+/* Meteor Lake Low Power Mode debug registers */
+#define MTL_LPM_PRI_OFFSET                     0x179C
+#define MTL_LPM_STATUS_LATCH_EN_OFFSET         0x16F8
+#define MTL_LPM_STATUS_OFFSET                  0x1700
+#define MTL_LPM_LIVE_STATUS_OFFSET             0x175C
+
 extern const char *pmc_lpm_modes[];
 
 struct pmc_bit_map {
@@ -383,6 +393,7 @@ extern const struct pmc_bit_map adl_vnn_req_status_3_map[];
 extern const struct pmc_bit_map adl_vnn_misc_status_map[];
 extern const struct pmc_bit_map *adl_lpm_maps[];
 extern const struct pmc_reg_map adl_reg_map;
+extern const struct pmc_reg_map mtl_reg_map;
 
 extern void pmc_core_get_tgl_lpm_reqs(struct platform_device *pdev);
 extern int pmc_core_send_ltr_ignore(struct pmc_dev *pmcdev, u32 value);
@@ -392,8 +403,10 @@ void cnp_core_init(struct pmc_dev *pmcdev);
 void icl_core_init(struct pmc_dev *pmcdev);
 void tgl_core_init(struct pmc_dev *pmcdev);
 void adl_core_init(struct pmc_dev *pmcdev);
+void mtl_core_init(struct pmc_dev *pmcdev);
 void tgl_core_configure(struct pmc_dev *pmcdev);
 void adl_core_configure(struct pmc_dev *pmcdev);
+void mtl_core_configure(struct pmc_dev *pmcdev);
 
 #define pmc_for_each_mode(i, mode, pmcdev)             \
        for (i = 0, mode = pmcdev->lpm_en_modes[i];     \

diff --git a/drivers/platform/x86/intel/pmc/mtl.c b/drivers/platform/x86/intel/pmc/mtl.c
new file mode 100644 (file)
index 0000000..eeb3bd8
--- /dev/null
+++ b/drivers/platform/x86/intel/pmc/mtl.c
@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * This file contains platform specific structure definitions
+ * and init function used by Meteor Lake PCH.
+ *
+ * Copyright (c) 2022, Intel Corporation.
+ * All Rights Reserved.
+ *
+ */
+
+#include "core.h"
+
+const struct pmc_reg_map mtl_reg_map = {
+       .pfear_sts = ext_tgl_pfear_map,
+       .slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
+       .slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP,
+       .ltr_show_sts = adl_ltr_show_map,
+       .msr_sts = msr_map,
+       .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
+       .regmap_length = CNP_PMC_MMIO_REG_LEN,
+       .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
+       .ppfear_buckets = ICL_PPFEAR_NUM_ENTRIES,
+       .pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
+       .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
+       .ltr_ignore_max = ADL_NUM_IP_IGN_ALLOWED,
+       .lpm_num_modes = ADL_LPM_NUM_MODES,
+       .lpm_num_maps = ADL_LPM_NUM_MAPS,
+       .lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2,
+       .etr3_offset = ETR3_OFFSET,
+       .lpm_sts_latch_en_offset = MTL_LPM_STATUS_LATCH_EN_OFFSET,
+       .lpm_priority_offset = MTL_LPM_PRI_OFFSET,
+       .lpm_en_offset = MTL_LPM_EN_OFFSET,
+       .lpm_residency_offset = MTL_LPM_RESIDENCY_OFFSET,
+       .lpm_sts = adl_lpm_maps,
+       .lpm_status_offset = MTL_LPM_STATUS_OFFSET,
+       .lpm_live_status_offset = MTL_LPM_LIVE_STATUS_OFFSET,
+};
+
+void mtl_core_configure(struct pmc_dev *pmcdev)
+{
+       /* Due to a hardware limitation, the GBE LTR blocks PC10
+        * when a cable is attached. Tell the PMC to ignore it.
+        */
+       dev_dbg(&pmcdev->pdev->dev, "ignoring GBE LTR\n");
+       pmc_core_send_ltr_ignore(pmcdev, 3);
+}
+
+void mtl_core_init(struct pmc_dev *pmcdev)
+{
+       pmcdev->map = &mtl_reg_map;
+       pmcdev->core_configure = mtl_core_configure;
+}