pmdomain: mediatek: Add support for MT8365

Add the needed board data to support MT8365 SoC.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
Tested-by: Alexandre Mergnat <amergnat@baylibre.com>
Link: https://lore.kernel.org/r/20230918093751.1188668-9-msp@baylibre.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>

diff --git a/drivers/pmdomain/mediatek/mt8365-pm-domains.h b/drivers/pmdomain/mediatek/mt8365-pm-domains.h
new file mode 100644 (file)
index 0000000..3d83d49
--- /dev/null
+++ b/drivers/pmdomain/mediatek/mt8365-pm-domains.h
@@ -0,0 +1,197 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_MEDIATEK_MT8365_PM_DOMAINS_H
+#define __SOC_MEDIATEK_MT8365_PM_DOMAINS_H
+
+#include "mtk-pm-domains.h"
+#include <dt-bindings/power/mediatek,mt8365-power.h>
+
+/*
+ * MT8365 power domain support
+ */
+
+#define MT8365_BUS_PROT_INFRA_WR_TOPAXI(_mask)                         \
+               BUS_PROT_WR(INFRA, _mask,                               \
+                           MT8365_INFRA_TOPAXI_PROTECTEN_SET,          \
+                           MT8365_INFRA_TOPAXI_PROTECTEN_CLR,          \
+                           MT8365_INFRA_TOPAXI_PROTECTEN_STA1)
+
+#define MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(_mask)                       \
+               BUS_PROT_WR(INFRA, _mask,                               \
+                           MT8365_INFRA_TOPAXI_PROTECTEN_1_SET,        \
+                           MT8365_INFRA_TOPAXI_PROTECTEN_1_CLR,        \
+                           MT8365_INFRA_TOPAXI_PROTECTEN_1_STA1)
+
+#define MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(port)                     \
+               BUS_PROT_WR(SMI, BIT(port),                             \
+                           MT8365_SMI_COMMON_CLAMP_EN_SET,             \
+                           MT8365_SMI_COMMON_CLAMP_EN_CLR,             \
+                           MT8365_SMI_COMMON_CLAMP_EN)
+
+#define MT8365_BUS_PROT_WAY_EN(_set_mask, _set, _sta_mask, _sta)       \
+               _BUS_PROT(_set_mask, _set, _set, _sta_mask, _sta,       \
+                         BUS_PROT_COMPONENT_INFRA |                    \
+                         BUS_PROT_STA_COMPONENT_INFRA_NAO |            \
+                         BUS_PROT_INVERTED |                           \
+                         BUS_PROT_REG_UPDATE)
+
+static const struct scpsys_domain_data scpsys_domain_data_mt8365[] = {
+       [MT8365_POWER_DOMAIN_MM] = {
+               .name = "mm",
+               .sta_mask = PWR_STATUS_DISP,
+               .ctl_offs = 0x30c,
+               .pwr_sta_offs = 0x0180,
+               .pwr_sta2nd_offs = 0x0184,
+               .sram_pdn_bits = GENMASK(8, 8),
+               .sram_pdn_ack_bits = GENMASK(12, 12),
+               .bp_cfg = {
+                       MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
+                               MT8365_INFRA_TOPAXI_PROTECTEN_1_MM2INFRA_AXI_GALS_MST_0 |
+                               MT8365_INFRA_TOPAXI_PROTECTEN_1_MM2INFRA_AXI_GALS_MST_1),
+                       MT8365_BUS_PROT_INFRA_WR_TOPAXI(
+                               MT8365_INFRA_TOPAXI_PROTECTEN_MM_M0 |
+                               MT8365_INFRA_TOPAXI_PROTECTEN_MDMCU_M1 |
+                               MT8365_INFRA_TOPAXI_PROTECTEN_MM2INFRA_AXI_GALS_SLV_0 |
+                               MT8365_INFRA_TOPAXI_PROTECTEN_MM2INFRA_AXI_GALS_SLV_1),
+                       MT8365_BUS_PROT_WAY_EN(
+                               MT8365_INFRA_TOPAXI_SI0_WAY_EN_MMAPB_S,
+                               MT8365_INFRA_TOPAXI_SI0_CTL,
+                               MT8365_INFRA_NAO_TOPAXI_SI0_CTRL_UPDATED,
+                               MT8365_INFRA_NAO_TOPAXI_SI0_STA),
+                       MT8365_BUS_PROT_WAY_EN(
+                               MT8365_INFRA_TOPAXI_SI2_WAY_EN_PERI_M1,
+                               MT8365_INFRA_TOPAXI_SI2_CTL,
+                               MT8365_INFRA_NAO_TOPAXI_SI2_CTRL_UPDATED,
+                               MT8365_INFRA_NAO_TOPAXI_SI2_STA),
+                       MT8365_BUS_PROT_INFRA_WR_TOPAXI(
+                               MT8365_INFRA_TOPAXI_PROTECTEN_MMAPB_S),
+               },
+               .caps = MTK_SCPD_STRICT_BUS_PROTECTION | MTK_SCPD_HAS_INFRA_NAO,
+       },
+       [MT8365_POWER_DOMAIN_VENC] = {
+               .name = "venc",
+               .sta_mask = PWR_STATUS_VENC,
+               .ctl_offs = 0x0304,
+               .pwr_sta_offs = 0x0180,
+               .pwr_sta2nd_offs = 0x0184,
+               .sram_pdn_bits = GENMASK(8, 8),
+               .sram_pdn_ack_bits = GENMASK(12, 12),
+               .bp_cfg = {
+                       MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(1),
+               },
+       },
+       [MT8365_POWER_DOMAIN_AUDIO] = {
+               .name = "audio",
+               .sta_mask = PWR_STATUS_AUDIO,
+               .ctl_offs = 0x0314,
+               .pwr_sta_offs = 0x0180,
+               .pwr_sta2nd_offs = 0x0184,
+               .sram_pdn_bits = GENMASK(12, 8),
+               .sram_pdn_ack_bits = GENMASK(17, 13),
+               .bp_cfg = {
+                       MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
+                               MT8365_INFRA_TOPAXI_PROTECTEN_1_PWRDNREQ_MP1_L2C_AFIFO |
+                               MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_AUDIO_M),
+               },
+               .caps = MTK_SCPD_ACTIVE_WAKEUP,
+       },
+       [MT8365_POWER_DOMAIN_CONN] = {
+               .name = "conn",
+               .sta_mask = PWR_STATUS_CONN,
+               .ctl_offs = 0x032c,
+               .pwr_sta_offs = 0x0180,
+               .pwr_sta2nd_offs = 0x0184,
+               .sram_pdn_bits = 0,
+               .sram_pdn_ack_bits = 0,
+               .bp_cfg = {
+                       MT8365_BUS_PROT_INFRA_WR_TOPAXI(
+                               MT8365_INFRA_TOPAXI_PROTECTEN_AP2CONN_AHB),
+                       MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
+                               MT8365_INFRA_TOPAXI_PROTECTEN_1_CONN2INFRA_AXI_GALS_MST),
+                       MT8365_BUS_PROT_INFRA_WR_TOPAXI(
+                               MT8365_INFRA_TOPAXI_PROTECTEN_CONN2INFRA_AHB),
+                       MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
+                               MT8365_INFRA_TOPAXI_PROTECTEN_1_INFRA2CONN_AHB_GALS_SLV),
+               },
+               .caps = MTK_SCPD_ACTIVE_WAKEUP | MTK_SCPD_KEEP_DEFAULT_OFF,
+       },
+       [MT8365_POWER_DOMAIN_MFG] = {
+               .name = "mfg",
+               .sta_mask = PWR_STATUS_MFG,
+               .ctl_offs = 0x0338,
+               .pwr_sta_offs = 0x0180,
+               .pwr_sta2nd_offs = 0x0184,
+               .sram_pdn_bits = GENMASK(9, 8),
+               .sram_pdn_ack_bits = GENMASK(13, 12),
+               .bp_cfg = {
+                       MT8365_BUS_PROT_INFRA_WR_TOPAXI(BIT(25)),
+                       MT8365_BUS_PROT_INFRA_WR_TOPAXI(
+                               MT8365_INFRA_TOPAXI_PROTECTEN_MFG_M0 |
+                               MT8365_INFRA_TOPAXI_PROTECTEN_INFRA2MFG),
+               },
+       },
+       [MT8365_POWER_DOMAIN_CAM] = {
+               .name = "cam",
+               .sta_mask = BIT(25),
+               .ctl_offs = 0x0344,
+               .pwr_sta_offs = 0x0180,
+               .pwr_sta2nd_offs = 0x0184,
+               .sram_pdn_bits = GENMASK(9, 8),
+               .sram_pdn_ack_bits = GENMASK(13, 12),
+               .bp_cfg = {
+                       MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
+                               MT8365_INFRA_TOPAXI_PROTECTEN_1_CAM2MM_AXI_GALS_MST),
+                       MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(2),
+               },
+       },
+       [MT8365_POWER_DOMAIN_VDEC] = {
+               .name = "vdec",
+               .sta_mask = BIT(31),
+               .ctl_offs = 0x0370,
+               .pwr_sta_offs = 0x0180,
+               .pwr_sta2nd_offs = 0x0184,
+               .sram_pdn_bits = GENMASK(8, 8),
+               .sram_pdn_ack_bits = GENMASK(12, 12),
+               .bp_cfg = {
+                       MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(3),
+               },
+       },
+       [MT8365_POWER_DOMAIN_APU] = {
+               .name = "apu",
+               .sta_mask = BIT(16),
+               .ctl_offs = 0x0378,
+               .pwr_sta_offs = 0x0180,
+               .pwr_sta2nd_offs = 0x0184,
+               .sram_pdn_bits = GENMASK(14, 8),
+               .sram_pdn_ack_bits = GENMASK(21, 15),
+               .bp_cfg = {
+                       MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
+                               MT8365_INFRA_TOPAXI_PROTECTEN_1_APU2AP |
+                               MT8365_INFRA_TOPAXI_PROTECTEN_1_APU_CBIP_GALS_MST),
+                       MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(4),
+               },
+       },
+       [MT8365_POWER_DOMAIN_DSP] = {
+               .name = "dsp",
+               .sta_mask = BIT(17),
+               .ctl_offs = 0x037C,
+               .pwr_sta_offs = 0x0180,
+               .pwr_sta2nd_offs = 0x0184,
+               .sram_pdn_bits = GENMASK(11, 8),
+               .sram_pdn_ack_bits = GENMASK(15, 12),
+               .bp_cfg = {
+                       MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
+                               MT8365_INFRA_TOPAXI_PROTECTEN_1_PWRDNREQ_INFRA_GALS_ADB |
+                               MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_DSP_M |
+                               MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_DSP_S),
+               },
+               .caps = MTK_SCPD_ACTIVE_WAKEUP,
+       },
+};
+
+static const struct scpsys_soc_data mt8365_scpsys_data = {
+       .domains_data = scpsys_domain_data_mt8365,
+       .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8365),
+};
+
+#endif /* __SOC_MEDIATEK_MT8365_PM_DOMAINS_H */

diff --git a/drivers/pmdomain/mediatek/mtk-pm-domains.c b/drivers/pmdomain/mediatek/mtk-pm-domains.c
index 69cdf6ff00b884d5ff5dd2f466cc4f81f81357d2..e26dc17d07ad71d8398044670227c93a6bdd4427 100644 (file)
--- a/drivers/pmdomain/mediatek/mtk-pm-domains.c
+++ b/drivers/pmdomain/mediatek/mtk-pm-domains.c
@@ -24,6 +24,7 @@
 #include "mt8188-pm-domains.h"
 #include "mt8192-pm-domains.h"
 #include "mt8195-pm-domains.h"
+#include "mt8365-pm-domains.h"
 
 #define MTK_POLL_DELAY_US              10
 #define MTK_POLL_TIMEOUT               USEC_PER_SEC
@@ -652,6 +653,10 @@ static const struct of_device_id scpsys_of_match[] = {
                .compatible = "mediatek,mt8195-power-controller",
                .data = &mt8195_scpsys_data,
        },
+       {
+               .compatible = "mediatek,mt8365-power-controller",
+               .data = &mt8365_scpsys_data,
+       },
        { }
 };
 

diff --git a/include/linux/soc/mediatek/infracfg.h b/include/linux/soc/mediatek/infracfg.h
index 07f67b3d8e970a335574cc83527f9d79a42ab69b..6c6cccc848f48ff59c2db7fc625c74709f0a0d93 100644 (file)
--- a/include/linux/soc/mediatek/infracfg.h
+++ b/include/linux/soc/mediatek/infracfg.h
@@ -2,6 +2,47 @@
 #ifndef __SOC_MEDIATEK_INFRACFG_H
 #define __SOC_MEDIATEK_INFRACFG_H
 
+#define MT8365_INFRA_TOPAXI_PROTECTEN_STA1                             0x228
+#define MT8365_INFRA_TOPAXI_PROTECTEN_SET                              0x2a0
+#define MT8365_INFRA_TOPAXI_PROTECTEN_CLR                              0x2a4
+#define MT8365_INFRA_TOPAXI_PROTECTEN_MM_M0                            BIT(1)
+#define MT8365_INFRA_TOPAXI_PROTECTEN_MDMCU_M1                         BIT(2)
+#define MT8365_INFRA_TOPAXI_PROTECTEN_MMAPB_S                          BIT(6)
+#define MT8365_INFRA_TOPAXI_PROTECTEN_MM2INFRA_AXI_GALS_SLV_0          BIT(10)
+#define MT8365_INFRA_TOPAXI_PROTECTEN_MM2INFRA_AXI_GALS_SLV_1          BIT(11)
+#define MT8365_INFRA_TOPAXI_PROTECTEN_AP2CONN_AHB                      BIT(13)
+#define MT8365_INFRA_TOPAXI_PROTECTEN_CONN2INFRA_AHB                   BIT(14)
+#define MT8365_INFRA_TOPAXI_PROTECTEN_MFG_M0                           BIT(21)
+#define MT8365_INFRA_TOPAXI_PROTECTEN_INFRA2MFG                        BIT(22)
+#define MT8365_INFRA_TOPAXI_PROTECTEN_1_STA1                           0x258
+#define MT8365_INFRA_TOPAXI_PROTECTEN_1_SET                            0x2a8
+#define MT8365_INFRA_TOPAXI_PROTECTEN_1_CLR                            0x2ac
+#define MT8365_INFRA_TOPAXI_PROTECTEN_1_APU2AP                         BIT(2)
+#define MT8365_INFRA_TOPAXI_PROTECTEN_1_MM2INFRA_AXI_GALS_MST_0        BIT(16)
+#define MT8365_INFRA_TOPAXI_PROTECTEN_1_MM2INFRA_AXI_GALS_MST_1        BIT(17)
+#define MT8365_INFRA_TOPAXI_PROTECTEN_1_CONN2INFRA_AXI_GALS_MST        BIT(18)
+#define MT8365_INFRA_TOPAXI_PROTECTEN_1_CAM2MM_AXI_GALS_MST            BIT(19)
+#define MT8365_INFRA_TOPAXI_PROTECTEN_1_APU_CBIP_GALS_MST              BIT(20)
+#define MT8365_INFRA_TOPAXI_PROTECTEN_1_INFRA2CONN_AHB_GALS_SLV        BIT(21)
+#define MT8365_INFRA_TOPAXI_PROTECTEN_1_PWRDNREQ_INFRA_GALS_ADB        BIT(24)
+#define MT8365_INFRA_TOPAXI_PROTECTEN_1_PWRDNREQ_MP1_L2C_AFIFO         BIT(27)
+#define MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_AUDIO_M              BIT(28)
+#define MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_DSP_M                BIT(30)
+#define MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_DSP_S                BIT(31)
+
+#define MT8365_INFRA_NAO_TOPAXI_SI0_STA                                        0x0
+#define MT8365_INFRA_NAO_TOPAXI_SI0_CTRL_UPDATED                       BIT(24)
+#define MT8365_INFRA_NAO_TOPAXI_SI2_STA                                        0x28
+#define MT8365_INFRA_NAO_TOPAXI_SI2_CTRL_UPDATED                       BIT(14)
+#define MT8365_INFRA_TOPAXI_SI0_CTL                                    0x200
+#define MT8365_INFRA_TOPAXI_SI0_WAY_EN_MMAPB_S                         BIT(6)
+#define MT8365_INFRA_TOPAXI_SI2_CTL                                    0x234
+#define MT8365_INFRA_TOPAXI_SI2_WAY_EN_PERI_M1                         BIT(5)
+
+#define MT8365_SMI_COMMON_CLAMP_EN                     0x3c0
+#define MT8365_SMI_COMMON_CLAMP_EN_SET                 0x3c4
+#define MT8365_SMI_COMMON_CLAMP_EN_CLR                 0x3c8
+
 #define MT8195_TOP_AXI_PROT_EN_STA1                     0x228
 #define MT8195_TOP_AXI_PROT_EN_1_STA1                   0x258
 #define MT8195_TOP_AXI_PROT_EN_SET                     0x2a0