drm/amdgpu: add PSP loading support for VPE
authorLang Yu <Lang.Yu@amd.com>
Tue, 9 May 2023 00:26:37 +0000 (08:26 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 31 Aug 2023 20:34:10 +0000 (16:34 -0400)
Add PSP loading support for Video Processing Engine.

Signed-off-by: Lang Yu <Lang.Yu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

index 75be1ca6155c69a67cacecbee3e6016f28e1a58d..e3b52f4436a777991445a80ab66f30fe72959f4d 100644 (file)
@@ -749,6 +749,7 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev,
        const struct mes_firmware_header_v1_0 *mes_hdr = NULL;
        const struct sdma_firmware_header_v2_0 *sdma_hdr = NULL;
        const struct imu_firmware_header_v1_0 *imu_hdr = NULL;
+       const struct vpe_firmware_header_v1_0 *vpe_hdr = NULL;
        u8 *ucode_addr;
 
        if (!ucode->fw)
@@ -768,6 +769,7 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev,
        mes_hdr = (const struct mes_firmware_header_v1_0 *)ucode->fw->data;
        sdma_hdr = (const struct sdma_firmware_header_v2_0 *)ucode->fw->data;
        imu_hdr = (const struct imu_firmware_header_v1_0 *)ucode->fw->data;
+       vpe_hdr = (const struct vpe_firmware_header_v1_0 *)ucode->fw->data;
 
        if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
                switch (ucode->ucode_id) {
@@ -950,6 +952,16 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev,
                        ucode_addr = (u8 *)ucode->fw->data +
                                le32_to_cpu(cpv2_hdr->data_offset_bytes);
                        break;
+               case AMDGPU_UCODE_ID_VPE_CTX:
+                       ucode->ucode_size = le32_to_cpu(vpe_hdr->ctx_ucode_size_bytes);
+                       ucode_addr = (u8 *)ucode->fw->data +
+                               le32_to_cpu(vpe_hdr->header.ucode_array_offset_bytes);
+                       break;
+               case AMDGPU_UCODE_ID_VPE_CTL:
+                       ucode->ucode_size = le32_to_cpu(vpe_hdr->ctl_ucode_size_bytes);
+                       ucode_addr = (u8 *)ucode->fw->data +
+                               le32_to_cpu(vpe_hdr->ctl_ucode_offset);
+                       break;
                default:
                        ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes);
                        ucode_addr = (u8 *)ucode->fw->data +
index f573a44d5d87baa6ea983053f3c828bcdbd8d1c1..a84e03a9b0fcf8d9a4997e2edf9cbdbc48e0e76f 100644 (file)
@@ -56,6 +56,22 @@ int amdgpu_vpe_init_microcode(struct amdgpu_vpe *vpe)
        adev->vpe.fw_version = le32_to_cpu(vpe_hdr->header.ucode_version);
        adev->vpe.feature_version = le32_to_cpu(vpe_hdr->ucode_feature_version);
 
+       if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
+               struct amdgpu_firmware_info *info;
+
+               info = &adev->firmware.ucode[AMDGPU_UCODE_ID_VPE_CTX];
+               info->ucode_id = AMDGPU_UCODE_ID_VPE_CTX;
+               info->fw = adev->vpe.fw;
+               adev->firmware.fw_size +=
+                       ALIGN(le32_to_cpu(vpe_hdr->ctx_ucode_size_bytes), PAGE_SIZE);
+
+               info = &adev->firmware.ucode[AMDGPU_UCODE_ID_VPE_CTL];
+               info->ucode_id = AMDGPU_UCODE_ID_VPE_CTL;
+               info->fw = adev->vpe.fw;
+               adev->firmware.fw_size +=
+                       ALIGN(le32_to_cpu(vpe_hdr->ctl_ucode_size_bytes), PAGE_SIZE);
+       }
+
        return 0;
 out:
        dev_err(adev->dev, "fail to initialize vpe microcode\n");