drm/amdgpu/display: properly guard dc_dsc_stream_bandwidth_in_kbps

Move the function protoype to the right header and guard
the call with CONFIG_DRM_AMD_DC_DCN as DSC is only available
with DCN.

Fixes: 8c2f14c36f47ce ("drm/amd/display: Add changes for dsc bpp in 16ths and unify bw calculations")
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: Dillon Varone <dillon.varone@amd.com>
Cc: Stephen Rothwell <sfr@canb.auug.org.au>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 10e34e411e06bc8e55ca34e4a3d1bf2af49d0a68..f9a33dc52c4555ad6ac992cfe5c159f4e0838460 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -3498,17 +3498,17 @@ void dc_link_enable_hpd_filter(struct dc_link *link, bool enable)
        }
 }
 
-uint32_t dc_dsc_stream_bandwidth_in_kbps(uint32_t pix_clk_100hz, uint32_t bpp_x16);
-
 uint32_t dc_bandwidth_in_kbps_from_timing(
        const struct dc_crtc_timing *timing)
 {
        uint32_t bits_per_channel = 0;
        uint32_t kbps;
 
+#if defined(CONFIG_DRM_AMD_DC_DCN)
        if (timing->flags.DSC) {
                return dc_dsc_stream_bandwidth_in_kbps(timing->pix_clk_100hz, timing->dsc_cfg.bits_per_pixel);
        }
+#endif
 
        switch (timing->display_color_depth) {
        case COLOR_DEPTH_666:

diff --git a/drivers/gpu/drm/amd/display/dc/dc_dsc.h b/drivers/gpu/drm/amd/display/dc/dc_dsc.h
index 0c5d98524536a4e5e7302e601dcb76c324910d97..c51d2d961b7a531c11cc97150ecc3e67c2918ea0 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc_dsc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_dsc.h
@@ -88,4 +88,6 @@ void dc_dsc_policy_set_max_target_bpp_limit(uint32_t limit);
 
 void dc_dsc_policy_set_enable_dsc_when_not_needed(bool enable);
 
+uint32_t dc_dsc_stream_bandwidth_in_kbps(uint32_t pix_clk_100hz, uint32_t bpp_x16);
+
 #endif