bpf, arm: Optimize ALU ARSH K using asr immediate instruction

This patch adds an optimization that uses the asr immediate instruction
for BPF_ALU BPF_ARSH BPF_K, rather than loading the immediate to
a temporary register. This is similar to existing code for handling
BPF_ALU BPF_{LSH,RSH} BPF_K. This optimization saves two instructions
and is more consistent with LSH and RSH.

Example of the code generated for BPF_ALU32_IMM(BPF_ARSH, BPF_REG_0, 5)
before the optimization:

  2c:  mov    r8, #5
  30:  mov    r9, #0
  34:  asr    r0, r0, r8

and after optimization:

  2c:  asr    r0, r0, #5

Tested on QEMU using lib/test_bpf and test_verifier.

Co-developed-by: Xi Wang <xi.wang@gmail.com>
Signed-off-by: Xi Wang <xi.wang@gmail.com>
Signed-off-by: Luke Nelson <luke.r.nels@gmail.com>
Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
Link: https://lore.kernel.org/bpf/20200501020210.32294-3-luke.r.nels@gmail.com

diff --git a/arch/arm/net/bpf_jit_32.c b/arch/arm/net/bpf_jit_32.c
index 48b89211ee5c3d3b3ea3f96b6405fbe794434272..0207b6ea6e8a0b3833f6b5376cc7c1fe75740358 100644 (file)
--- a/arch/arm/net/bpf_jit_32.c
+++ b/arch/arm/net/bpf_jit_32.c
@@ -795,6 +795,9 @@ static inline void emit_a32_alu_i(const s8 dst, const u32 val,
        case BPF_RSH:
                emit(ARM_LSR_I(rd, rd, val), ctx);
                break;
+       case BPF_ARSH:
+               emit(ARM_ASR_I(rd, rd, val), ctx);
+               break;
        case BPF_NEG:
                emit(ARM_RSB_I(rd, rd, val), ctx);
                break;
@@ -1408,7 +1411,6 @@ static int build_insn(const struct bpf_insn *insn, struct jit_ctx *ctx)
        case BPF_ALU | BPF_MUL | BPF_X:
        case BPF_ALU | BPF_LSH | BPF_X:
        case BPF_ALU | BPF_RSH | BPF_X:
-       case BPF_ALU | BPF_ARSH | BPF_K:
        case BPF_ALU | BPF_ARSH | BPF_X:
        case BPF_ALU64 | BPF_ADD | BPF_K:
        case BPF_ALU64 | BPF_ADD | BPF_X:
@@ -1465,10 +1467,12 @@ static int build_insn(const struct bpf_insn *insn, struct jit_ctx *ctx)
        case BPF_ALU64 | BPF_MOD | BPF_K:
        case BPF_ALU64 | BPF_MOD | BPF_X:
                goto notyet;
-       /* dst = dst >> imm */
        /* dst = dst << imm */
-       case BPF_ALU | BPF_RSH | BPF_K:
+       /* dst = dst >> imm */
+       /* dst = dst >> imm (signed) */
        case BPF_ALU | BPF_LSH | BPF_K:
+       case BPF_ALU | BPF_RSH | BPF_K:
+       case BPF_ALU | BPF_ARSH | BPF_K:
                if (unlikely(imm > 31))
                        return -EINVAL;
                if (imm)

diff --git a/arch/arm/net/bpf_jit_32.h b/arch/arm/net/bpf_jit_32.h
index fb67cbc589e049e89b4d39eaa2fba13fc3c791e1..e0b593a1498d11aa46e077dfab85caeb7d957e82 100644 (file)
--- a/arch/arm/net/bpf_jit_32.h
+++ b/arch/arm/net/bpf_jit_32.h
@@ -94,6 +94,9 @@
 #define ARM_INST_LSR_I         0x01a00020
 #define ARM_INST_LSR_R         0x01a00030
 
+#define ARM_INST_ASR_I         0x01a00040
+#define ARM_INST_ASR_R         0x01a00050
+
 #define ARM_INST_MOV_R         0x01a00000
 #define ARM_INST_MOVS_R                0x01b00000
 #define ARM_INST_MOV_I         0x03a00000