clk: imx: imx8mn: fix a53 cpu clock

The A53 CCM clk root only accepts input up to 1GHz, CCM A53 root
signoff timing is 1Ghz, however the A53 core which sources from CCM
root could run above 1GHz which voilates the CCM.

There is a CORE_SEL slice before A53 core, we need configure the
CORE_SEL slice source from ARM PLL, not A53 CCM clk root.

The A53 CCM clk root should only be used when need to change ARM PLL
frequency.

Add arm_a53_core clk that could source from arm_a53_div and arm_pll_out.
Configure a53 ccm root sources from 800MHz sys pll
Configure a53 core sources from arm_pll_out
Mark arm_a53_core as critical clk.

Fixes: 96d6392b54db ("clk: imx: Add support for i.MX8MN clock driver")
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
index fb47f86e35e8c1e7258353787892232cfc8e4f14..83618affca8bfbfce2f2f7e1137acf6facff67eb 100644 (file)
--- a/drivers/clk/imx/clk-imx8mn.c
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -38,6 +38,8 @@ static const char * const imx8mn_a53_sels[] = {"osc_24m", "arm_pll_out", "sys_pl
                                               "sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m",
                                               "audio_pll1_out", "sys_pll3_out", };
 
+static const char * const imx8mn_a53_core_sels[] = {"arm_a53_div", "arm_pll_out", };
+
 static const char * const imx8mn_gpu_core_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m",
                                                    "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out",
                                                    "video_pll1_out", "audio_pll2_out", };
@@ -425,6 +427,9 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
        hws[IMX8MN_CLK_GPU_SHADER_CG] = hws[IMX8MN_CLK_GPU_SHADER];
        hws[IMX8MN_CLK_GPU_SHADER_DIV] = hws[IMX8MN_CLK_GPU_SHADER];
 
+       /* CORE SEL */
+       hws[IMX8MN_CLK_A53_CORE] = imx_clk_hw_mux2_flags("arm_a53_core", base + 0x9880, 24, 1, imx8mn_a53_core_sels, ARRAY_SIZE(imx8mn_a53_core_sels), CLK_IS_CRITICAL);
+
        /* BUS */
        hws[IMX8MN_CLK_MAIN_AXI] = imx8m_clk_hw_composite_critical("main_axi", imx8mn_main_axi_sels, base + 0x8800);
        hws[IMX8MN_CLK_ENET_AXI] = imx8m_clk_hw_composite("enet_axi", imx8mn_enet_axi_sels, base + 0x8880);
@@ -554,11 +559,14 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
 
        hws[IMX8MN_CLK_DRAM_ALT_ROOT] = imx_clk_hw_fixed_factor("dram_alt_root", "dram_alt", 1, 4);
 
-       hws[IMX8MN_CLK_ARM] = imx_clk_hw_cpu("arm", "arm_a53_div",
-                                          hws[IMX8MN_CLK_A53_DIV]->clk,
-                                          hws[IMX8MN_CLK_A53_SRC]->clk,
+       clk_hw_set_parent(hws[IMX8MN_CLK_A53_SRC], hws[IMX8MN_SYS_PLL1_800M]);
+       clk_hw_set_parent(hws[IMX8MN_CLK_A53_CORE], hws[IMX8MN_ARM_PLL_OUT]);
+
+       hws[IMX8MN_CLK_ARM] = imx_clk_hw_cpu("arm", "arm_a53_core",
+                                          hws[IMX8MN_CLK_A53_CORE]->clk,
+                                          hws[IMX8MN_CLK_A53_CORE]->clk,
                                           hws[IMX8MN_ARM_PLL_OUT]->clk,
-                                          hws[IMX8MN_SYS_PLL1_800M]->clk);
+                                          hws[IMX8MN_CLK_A53_DIV]->clk);
 
        imx_check_clk_hws(hws, IMX8MN_CLK_END);
 

diff --git a/include/dt-bindings/clock/imx8mn-clock.h b/include/dt-bindings/clock/imx8mn-clock.h
index c42a22d3cf7cbbdd392a0d5eb0944b67f244bcc6..6c4364c01c5022c5d433350d72187f2eb163c1f0 100644 (file)
--- a/include/dt-bindings/clock/imx8mn-clock.h
+++ b/include/dt-bindings/clock/imx8mn-clock.h
@@ -232,6 +232,8 @@
 #define IMX8MN_CLK_GPU_CORE                    212
 #define IMX8MN_CLK_GPU_SHADER                  213
 
-#define IMX8MN_CLK_END                         214
+#define IMX8MN_CLK_A53_CORE                    214
+
+#define IMX8MN_CLK_END                         215
 
 #endif