what we really want is a read or write that is guaranteed to be 64 bits
at a time, atomic64 operations are supported on all architectures
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
  */
 uint64_t amdgpu_mm_rreg64(struct amdgpu_device *adev, uint32_t reg)
 {
-       uint64_t ret;
-
        if ((reg * 4) < adev->rmmio_size)
-               ret = readq(((void __iomem *)adev->rmmio) + (reg * 4));
+               return atomic64_read((atomic64_t *)(adev->rmmio + (reg * 4)));
        else
                BUG();
-
-       return ret;
 }
 
 /**
 void amdgpu_mm_wreg64(struct amdgpu_device *adev, uint32_t reg, uint64_t v)
 {
        if ((reg * 4) < adev->rmmio_size)
-               writeq(v, ((void __iomem *)adev->rmmio) + (reg * 4));
+               atomic64_set((atomic64_t *)(adev->rmmio + (reg * 4)), v);
        else
                BUG();
 }