drm/i915/gt: Convert the leftover for_each_engine(gt)

Use the local gt for iterating over the available set of engines.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191018115331.8980-1-chris@chris-wilson.co.uk

diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
index 71184aa7289612e10b48301864dfb4a7d552403d..70f0e01a38b97599dd71bc5822177e7f29dffd2c 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -65,7 +65,7 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6)
 
        set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
        set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
-       for_each_engine(engine, rc6_to_gt(rc6)->i915, id)
+       for_each_engine(engine, rc6_to_gt(rc6), id)
                set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
 
        set(uncore, GUC_MAX_IDLE_COUNT, 0xA);
@@ -133,7 +133,7 @@ static void gen9_rc6_enable(struct intel_rc6 *rc6)
 
        set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
        set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
-       for_each_engine(engine, rc6_to_gt(rc6)->i915, id)
+       for_each_engine(engine, rc6_to_gt(rc6), id)
                set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
 
        set(uncore, GUC_MAX_IDLE_COUNT, 0xA);
@@ -192,7 +192,7 @@ static void gen8_rc6_enable(struct intel_rc6 *rc6)
        set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
        set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
        set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
-       for_each_engine(engine, rc6_to_gt(rc6)->i915, id)
+       for_each_engine(engine, rc6_to_gt(rc6), id)
                set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
        set(uncore, GEN6_RC_SLEEP, 0);
        set(uncore, GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
@@ -219,7 +219,7 @@ static void gen6_rc6_enable(struct intel_rc6 *rc6)
        set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000);
        set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25);
 
-       for_each_engine(engine, i915, id)
+       for_each_engine(engine, rc6_to_gt(rc6), id)
                set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
 
        set(uncore, GEN6_RC_SLEEP, 0);
@@ -344,7 +344,7 @@ static void chv_rc6_enable(struct intel_rc6 *rc6)
        set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
        set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
 
-       for_each_engine(engine, rc6_to_gt(rc6)->i915, id)
+       for_each_engine(engine, rc6_to_gt(rc6), id)
                set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
        set(uncore, GEN6_RC_SLEEP, 0);
 
@@ -371,7 +371,7 @@ static void vlv_rc6_enable(struct intel_rc6 *rc6)
        set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000);
        set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25);
 
-       for_each_engine(engine, rc6_to_gt(rc6)->i915, id)
+       for_each_engine(engine, rc6_to_gt(rc6), id)
                set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
 
        set(uncore, GEN6_RC6_THRESHOLD, 0x557);

diff --git a/drivers/gpu/drm/i915/gt/intel_ringbuffer.c b/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
index 311fdc0a21bc26d8287d36e2ebc2ca82ec6955ad..bf631f15aa781a36de3a106444662c634b8f2903 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
@@ -1609,7 +1609,7 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags)
                        struct intel_engine_cs *signaller;
 
                        *cs++ = MI_LOAD_REGISTER_IMM(num_engines);
-                       for_each_engine(signaller, i915, id) {
+                       for_each_engine(signaller, engine->gt, id) {
                                if (signaller == engine)
                                        continue;
 
@@ -1663,7 +1663,7 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags)
                        i915_reg_t last_reg = {}; /* keep gcc quiet */
 
                        *cs++ = MI_LOAD_REGISTER_IMM(num_engines);
-                       for_each_engine(signaller, i915, id) {
+                       for_each_engine(signaller, engine->gt, id) {
                                if (signaller == engine)
                                        continue;
 
@@ -1676,7 +1676,7 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags)
                        /* Insert a delay before the next switch! */
                        *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
                        *cs++ = i915_mmio_reg_offset(last_reg);
-                       *cs++ = intel_gt_scratch_offset(rq->engine->gt,
+                       *cs++ = intel_gt_scratch_offset(engine->gt,
                                                        INTEL_GT_SCRATCH_FIELD_DEFAULT);
                        *cs++ = MI_NOOP;
                }

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 0df057838a247cc01f7a64e9788bbfe66ac042cb..3148d5946b63c62ae5c81e324cf5992f8bf089f1 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1569,7 +1569,7 @@ static void gen7_ppgtt_enable(struct intel_gt *gt)
        }
        intel_uncore_write(uncore, GAM_ECOCHK, ecochk);
 
-       for_each_engine(engine, i915, id) {
+       for_each_engine(engine, gt, id) {
                /* GFX_MODE is per-ring on gen7+ */
                ENGINE_WRITE(engine,
                             RING_MODE_GEN7,

diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 144c32eed04568ae620b1d2518e920c9b2b409a2..85912917c062834947105ffa29f8eb412fa9f764 100644 (file)
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -301,7 +301,7 @@ engines_sample(struct intel_gt *gt, unsigned int period_ns)
        if ((i915->pmu.enable & ENGINE_SAMPLE_MASK) == 0)
                return;
 
-       for_each_engine(engine, i915, id) {
+       for_each_engine(engine, gt, id) {
                struct intel_engine_pmu *pmu = &engine->pmu;
                unsigned long flags;
                bool busy;