net: dsa: sja1105: Separate C22 and C45 transactions for T1 MDIO bus

The T1 MDIO bus driver can perform both C22 and C45 transfers. Create
separate functions for each and register the C45 versions using the
new API calls where appropriate.

Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

diff --git a/drivers/net/dsa/sja1105/sja1105_mdio.c b/drivers/net/dsa/sja1105/sja1105_mdio.c
index 8f1fcaf8e1d9715fc2efff4b8e640ad7a9566097..2fcb601cb4ebc14230c0ed84c4f84386c1155903 100644 (file)
--- a/drivers/net/dsa/sja1105/sja1105_mdio.c
+++ b/drivers/net/dsa/sja1105/sja1105_mdio.c
@@ -149,7 +149,7 @@ static u64 sja1105_base_t1_encode_addr(struct sja1105_private *priv,
        return regs->mdio_100base_t1 | (phy << 7) | (op << 5) | (xad << 0);
 }
 
-static int sja1105_base_t1_mdio_read(struct mii_bus *bus, int phy, int reg)
+static int sja1105_base_t1_mdio_read_c22(struct mii_bus *bus, int phy, int reg)
 {
        struct sja1105_mdio_private *mdio_priv = bus->priv;
        struct sja1105_private *priv = mdio_priv->priv;
@@ -157,30 +157,31 @@ static int sja1105_base_t1_mdio_read(struct mii_bus *bus, int phy, int reg)
        u32 tmp;
        int rc;
 
-       if (reg & MII_ADDR_C45) {
-               u16 mmd = (reg >> MII_DEVADDR_C45_SHIFT) & 0x1f;
-
-               addr = sja1105_base_t1_encode_addr(priv, phy, SJA1105_C45_ADDR,
-                                                  mmd);
+       addr = sja1105_base_t1_encode_addr(priv, phy, SJA1105_C22, reg & 0x1f);
 
-               tmp = reg & MII_REGADDR_C45_MASK;
+       rc = sja1105_xfer_u32(priv, SPI_READ, addr, &tmp, NULL);
+       if (rc < 0)
+               return rc;
 
-               rc = sja1105_xfer_u32(priv, SPI_WRITE, addr, &tmp, NULL);
-               if (rc < 0)
-                       return rc;
+       return tmp & 0xffff;
+}
 
-               addr = sja1105_base_t1_encode_addr(priv, phy, SJA1105_C45_DATA,
-                                                  mmd);
+static int sja1105_base_t1_mdio_read_c45(struct mii_bus *bus, int phy,
+                                        int mmd, int reg)
+{
+       struct sja1105_mdio_private *mdio_priv = bus->priv;
+       struct sja1105_private *priv = mdio_priv->priv;
+       u64 addr;
+       u32 tmp;
+       int rc;
 
-               rc = sja1105_xfer_u32(priv, SPI_READ, addr, &tmp, NULL);
-               if (rc < 0)
-                       return rc;
+       addr = sja1105_base_t1_encode_addr(priv, phy, SJA1105_C45_ADDR, mmd);
 
-               return tmp & 0xffff;
-       }
+       rc = sja1105_xfer_u32(priv, SPI_WRITE, addr, &reg, NULL);
+       if (rc < 0)
+               return rc;
 
-       /* Clause 22 read */
-       addr = sja1105_base_t1_encode_addr(priv, phy, SJA1105_C22, reg & 0x1f);
+       addr = sja1105_base_t1_encode_addr(priv, phy, SJA1105_C45_DATA, mmd);
 
        rc = sja1105_xfer_u32(priv, SPI_READ, addr, &tmp, NULL);
        if (rc < 0)
@@ -189,41 +190,37 @@ static int sja1105_base_t1_mdio_read(struct mii_bus *bus, int phy, int reg)
        return tmp & 0xffff;
 }
 
-static int sja1105_base_t1_mdio_write(struct mii_bus *bus, int phy, int reg,
-                                     u16 val)
+static int sja1105_base_t1_mdio_write_c22(struct mii_bus *bus, int phy, int reg,
+                                         u16 val)
 {
        struct sja1105_mdio_private *mdio_priv = bus->priv;
        struct sja1105_private *priv = mdio_priv->priv;
        u64 addr;
        u32 tmp;
-       int rc;
-
-       if (reg & MII_ADDR_C45) {
-               u16 mmd = (reg >> MII_DEVADDR_C45_SHIFT) & 0x1f;
-
-               addr = sja1105_base_t1_encode_addr(priv, phy, SJA1105_C45_ADDR,
-                                                  mmd);
 
-               tmp = reg & MII_REGADDR_C45_MASK;
+       addr = sja1105_base_t1_encode_addr(priv, phy, SJA1105_C22, reg & 0x1f);
 
-               rc = sja1105_xfer_u32(priv, SPI_WRITE, addr, &tmp, NULL);
-               if (rc < 0)
-                       return rc;
+       tmp = val & 0xffff;
 
-               addr = sja1105_base_t1_encode_addr(priv, phy, SJA1105_C45_DATA,
-                                                  mmd);
+       return sja1105_xfer_u32(priv, SPI_WRITE, addr, &tmp, NULL);
+}
 
-               tmp = val & 0xffff;
+static int sja1105_base_t1_mdio_write_c45(struct mii_bus *bus, int phy,
+                                         int mmd, int reg, u16 val)
+{
+       struct sja1105_mdio_private *mdio_priv = bus->priv;
+       struct sja1105_private *priv = mdio_priv->priv;
+       u64 addr;
+       u32 tmp;
+       int rc;
 
-               rc = sja1105_xfer_u32(priv, SPI_WRITE, addr, &tmp, NULL);
-               if (rc < 0)
-                       return rc;
+       addr = sja1105_base_t1_encode_addr(priv, phy, SJA1105_C45_ADDR, mmd);
 
-               return 0;
-       }
+       rc = sja1105_xfer_u32(priv, SPI_WRITE, addr, &reg, NULL);
+       if (rc < 0)
+               return rc;
 
-       /* Clause 22 write */
-       addr = sja1105_base_t1_encode_addr(priv, phy, SJA1105_C22, reg & 0x1f);
+       addr = sja1105_base_t1_encode_addr(priv, phy, SJA1105_C45_DATA, mmd);
 
        tmp = val & 0xffff;
 
@@ -342,8 +339,10 @@ static int sja1105_mdiobus_base_t1_register(struct sja1105_private *priv,
        bus->name = "SJA1110 100base-T1 MDIO bus";
        snprintf(bus->id, MII_BUS_ID_SIZE, "%s-base-t1",
                 dev_name(priv->ds->dev));
-       bus->read = sja1105_base_t1_mdio_read;
-       bus->write = sja1105_base_t1_mdio_write;
+       bus->read = sja1105_base_t1_mdio_read_c22;
+       bus->write = sja1105_base_t1_mdio_write_c22;
+       bus->read_c45 = sja1105_base_t1_mdio_read_c45;
+       bus->write_c45 = sja1105_base_t1_mdio_write_c45;
        bus->parent = priv->ds->dev;
        mdio_priv = bus->priv;
        mdio_priv->priv = priv;