arm64: zynqmp: Describe TI phy as ethernet-phy-id

TI DP83867 is using strapping based on MIO pins. Tristate setup can
influence PHY address. That's why switch description with ethernet-phy-id
compatible string which enable calling reset. PHY itself setups phy address
after power up or reset. Phy reset is done via gpio.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/b49904649a363f40dc9c4d3fa275e42129562082.1684767562.git.michal.simek@amd.com

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
index 230ef94d5dcb1313bf4ddd7ea7b744f0b0e8332e..f36353a51863357c510e7c922aaf28c4595c3854 100644 (file)
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
@@ -2,7 +2,8 @@
 /*
  * dts file for Xilinx ZynqMP ZCU102 RevA
  *
- * (C) Copyright 2015 - 2021, Xilinx, Inc.
+ * (C) Copyright 2015 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
  *
  * Michal Simek <michal.simek@amd.com>
  */
@@ -200,13 +201,19 @@
        phy-mode = "rgmii-id";
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_gem3_default>;
-       phy0: ethernet-phy@21 {
-               reg = <21>;
-               ti,rx-internal-delay = <0x8>;
-               ti,tx-internal-delay = <0xa>;
-               ti,fifo-depth = <0x1>;
-               ti,dp83867-rxctrl-strap-quirk;
-               /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */
+       mdio: mdio {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               phy0: ethernet-phy@21 {
+                       #phy-cells = <1>;
+                       compatible = "ethernet-phy-id2000.a231";
+                       reg = <21>;
+                       ti,rx-internal-delay = <0x8>;
+                       ti,tx-internal-delay = <0xa>;
+                       ti,fifo-depth = <0x1>;
+                       ti,dp83867-rxctrl-strap-quirk;
+                       reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;
+               };
        };
 };
 

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts
index 63419deb5b336157a7be08436ea415ab1a97d91c..3c28130909bc60268e26315367037db63161e3bb 100644 (file)
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts
@@ -2,7 +2,8 @@
 /*
  * dts file for Xilinx ZynqMP ZCU102 RevB
  *
- * (C) Copyright 2016 - 2021, Xilinx, Inc.
+ * (C) Copyright 2016 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
  *
  * Michal Simek <michal.simek@amd.com>
  */
@@ -16,16 +17,20 @@
 
 &gem3 {
        phy-handle = <&phyc>;
-       phyc: ethernet-phy@c {
-               reg = <0xc>;
-               ti,rx-internal-delay = <0x8>;
-               ti,tx-internal-delay = <0xa>;
-               ti,fifo-depth = <0x1>;
-               ti,dp83867-rxctrl-strap-quirk;
-               /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */
+       mdio: mdio {
+               phyc: ethernet-phy@c {
+                       #phy-cells = <0x1>;
+                       compatible = "ethernet-phy-id2000.a231";
+                       reg = <0xc>;
+                       ti,rx-internal-delay = <0x8>;
+                       ti,tx-internal-delay = <0xa>;
+                       ti,fifo-depth = <0x1>;
+                       ti,dp83867-rxctrl-strap-quirk;
+                       reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;
+               };
+               /* Cleanup from RevA */
+               /delete-node/ ethernet-phy@21;
        };
-       /* Cleanup from RevA */
-       /delete-node/ ethernet-phy@21;
 };
 
 /* Fix collision with u61 */

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
index d178a4f898c9420823a39ccc218ffacb43970c4f..3fd47725c2c84566e577068adf0030580f1331dc 100644 (file)
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
@@ -2,7 +2,8 @@
 /*
  * dts file for Xilinx ZynqMP ZCU104
  *
- * (C) Copyright 2017 - 2021, Xilinx, Inc.
+ * (C) Copyright 2017 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
  *
  * Michal Simek <michal.simek@amd.com>
  */
@@ -109,12 +110,19 @@
        phy-mode = "rgmii-id";
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_gem3_default>;
-       phy0: ethernet-phy@c {
-               reg = <0xc>;
-               ti,rx-internal-delay = <0x8>;
-               ti,tx-internal-delay = <0xa>;
-               ti,fifo-depth = <0x1>;
-               ti,dp83867-rxctrl-strap-quirk;
+       mdio: mdio {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               phy0: ethernet-phy@c {
+                       #phy-cells = <1>;
+                       compatible = "ethernet-phy-id2000.a231";
+                       reg = <0xc>;
+                       ti,rx-internal-delay = <0x8>;
+                       ti,tx-internal-delay = <0xa>;
+                       ti,fifo-depth = <0x1>;
+                       ti,dp83867-rxctrl-strap-quirk;
+                       reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;
+               };
        };
 };
 

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts
index 38b11594c0742b390ed0c75c667ed83eb7b9e012..4f6429caecff21581a29e837d5e0acd5a668a16f 100644 (file)
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts
@@ -2,7 +2,8 @@
 /*
  * dts file for Xilinx ZynqMP ZCU104
  *
- * (C) Copyright 2017 - 2021, Xilinx, Inc.
+ * (C) Copyright 2017 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
  *
  * Michal Simek <michal.simek@amd.com>
  */
@@ -114,12 +115,19 @@
        phy-mode = "rgmii-id";
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_gem3_default>;
-       phy0: ethernet-phy@c {
-               reg = <0xc>;
-               ti,rx-internal-delay = <0x8>;
-               ti,tx-internal-delay = <0xa>;
-               ti,fifo-depth = <0x1>;
-               ti,dp83867-rxctrl-strap-quirk;
+       mdio: mdio {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               phy0: ethernet-phy@c {
+                       #phy-cells = <1>;
+                       compatible = "ethernet-phy-id2000.a231";
+                       reg = <0xc>;
+                       ti,rx-internal-delay = <0x8>;
+                       ti,tx-internal-delay = <0xa>;
+                       ti,fifo-depth = <0x1>;
+                       ti,dp83867-rxctrl-strap-quirk;
+                       reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;
+               };
        };
 };
 

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
index 8af0879806cf06d9862657aae04db50475f530b6..8c3fa3fe28d5e414059c5e35a333ebdde05a8ddb 100644 (file)
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
@@ -2,7 +2,8 @@
 /*
  * dts file for Xilinx ZynqMP ZCU106
  *
- * (C) Copyright 2016 - 2021, Xilinx, Inc.
+ * (C) Copyright 2016 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
  *
  * Michal Simek <michal.simek@amd.com>
  */
@@ -212,12 +213,19 @@
        phy-mode = "rgmii-id";
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_gem3_default>;
-       phy0: ethernet-phy@c {
-               reg = <0xc>;
-               ti,rx-internal-delay = <0x8>;
-               ti,tx-internal-delay = <0xa>;
-               ti,fifo-depth = <0x1>;
-               ti,dp83867-rxctrl-strap-quirk;
+       mdio: mdio {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               phy0: ethernet-phy@c {
+                       #phy-cells = <1>;
+                       reg = <0xc>;
+                       compatible = "ethernet-phy-id2000.a231";
+                       ti,rx-internal-delay = <0x8>;
+                       ti,tx-internal-delay = <0xa>;
+                       ti,fifo-depth = <0x1>;
+                       ti,dp83867-rxctrl-strap-quirk;
+                       reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;
+               };
        };
 };
 

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
index f76687914e309749450ff64fc390834e2e81c45d..0d9b6081dff69d9b62c401264a944e1e5612b1cd 100644 (file)
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
@@ -2,7 +2,8 @@
 /*
  * dts file for Xilinx ZynqMP ZCU111
  *
- * (C) Copyright 2017 - 2021, Xilinx, Inc.
+ * (C) Copyright 2017 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
  *
  * Michal Simek <michal.simek@amd.com>
  */
@@ -172,12 +173,19 @@
        phy-mode = "rgmii-id";
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_gem3_default>;
-       phy0: ethernet-phy@c {
-               reg = <0xc>;
-               ti,rx-internal-delay = <0x8>;
-               ti,tx-internal-delay = <0xa>;
-               ti,fifo-depth = <0x1>;
-               ti,dp83867-rxctrl-strap-quirk;
+       mdio: mdio {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               phy0: ethernet-phy@c {
+                       #phy-cells = <1>;
+                       compatible = "ethernet-phy-id2000.a231";
+                       reg = <0xc>;
+                       ti,rx-internal-delay = <0x8>;
+                       ti,tx-internal-delay = <0xa>;
+                       ti,fifo-depth = <0x1>;
+                       ti,dp83867-rxctrl-strap-quirk;
+                       reset-gpios = <&tca6416_u22 6 GPIO_ACTIVE_LOW>;
+               };
        };
 };