select CLKSRC_SAMSUNG_PWM
select GPIO_SAMSUNG
select GPIOLIB
+ select IRQ_DOMAIN
select S3C2410_WATCHDOG
select SAMSUNG_ATAGS
+ select SPARSE_IRQ
select USE_OF
select WATCHDOG
help
#include <asm/mach/irq.h>
#include "map.h"
-#include <mach/irqs.h>
+#include "irqs.h"
#include "bast.h"
#include <asm/mach/irq.h>
#include "regs-irq.h"
-#include <mach/irqs.h>
+#include "irqs.h"
#include "bast.h"
#include <linux/gpio.h>
#include <linux/export.h>
-#include <mach/irqs.h>
+#include "irqs.h"
#include "map.h"
#include "devs.h"
#include <asm/mach/arch.h>
#include <asm/mach/irq.h>
#include "map.h"
-#include <mach/irqs.h>
+#include "irqs.h"
#include "devs.h"
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
-#include <mach/irqs.h>
+#include "irqs.h"
#include "map.h"
#include "gpio-samsung.h"
#include "gpio-cfg.h"
#include <asm/irq.h>
-#include <mach/irqs.h>
+#include "irqs.h"
#include "map.h"
#include "regs-gpio.h"
#include "gpio-samsung.h"
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2003-2005 Simtec Electronics
- * Ben Dooks <ben@simtec.co.uk>
- */
-
-
-#ifndef __ASM_ARCH_IRQS_H
-#define __ASM_ARCH_IRQS_H __FILE__
-
-/* we keep the first set of CPU IRQs out of the range of
- * the ISA space, so that the PC104 has them to itself
- * and we don't end up having to do horrible things to the
- * standard ISA drivers....
- */
-
-#define S3C2410_CPUIRQ_OFFSET (16)
-
-#define S3C2410_IRQ(x) ((x) + S3C2410_CPUIRQ_OFFSET)
-
-/* main cpu interrupts */
-#define IRQ_EINT0 S3C2410_IRQ(0) /* 16 */
-#define IRQ_EINT1 S3C2410_IRQ(1)
-#define IRQ_EINT2 S3C2410_IRQ(2)
-#define IRQ_EINT3 S3C2410_IRQ(3)
-#define IRQ_EINT4t7 S3C2410_IRQ(4) /* 20 */
-#define IRQ_EINT8t23 S3C2410_IRQ(5)
-#define IRQ_RESERVED6 S3C2410_IRQ(6) /* for s3c2410 */
-#define IRQ_CAM S3C2410_IRQ(6) /* for s3c2440,s3c2443 */
-#define IRQ_BATT_FLT S3C2410_IRQ(7)
-#define IRQ_TICK S3C2410_IRQ(8) /* 24 */
-#define IRQ_WDT S3C2410_IRQ(9) /* WDT/AC97 for s3c2443 */
-#define IRQ_TIMER0 S3C2410_IRQ(10)
-#define IRQ_TIMER1 S3C2410_IRQ(11)
-#define IRQ_TIMER2 S3C2410_IRQ(12)
-#define IRQ_TIMER3 S3C2410_IRQ(13)
-#define IRQ_TIMER4 S3C2410_IRQ(14)
-#define IRQ_UART2 S3C2410_IRQ(15)
-#define IRQ_LCD S3C2410_IRQ(16) /* 32 */
-#define IRQ_DMA0 S3C2410_IRQ(17) /* IRQ_DMA for s3c2443 */
-#define IRQ_DMA1 S3C2410_IRQ(18)
-#define IRQ_DMA2 S3C2410_IRQ(19)
-#define IRQ_DMA3 S3C2410_IRQ(20)
-#define IRQ_SDI S3C2410_IRQ(21)
-#define IRQ_SPI0 S3C2410_IRQ(22)
-#define IRQ_UART1 S3C2410_IRQ(23)
-#define IRQ_RESERVED24 S3C2410_IRQ(24) /* 40 */
-#define IRQ_NFCON S3C2410_IRQ(24) /* for s3c2440 */
-#define IRQ_USBD S3C2410_IRQ(25)
-#define IRQ_USBH S3C2410_IRQ(26)
-#define IRQ_IIC S3C2410_IRQ(27)
-#define IRQ_UART0 S3C2410_IRQ(28) /* 44 */
-#define IRQ_SPI1 S3C2410_IRQ(29)
-#define IRQ_RTC S3C2410_IRQ(30)
-#define IRQ_ADCPARENT S3C2410_IRQ(31)
-
-/* interrupts generated from the external interrupts sources */
-#define IRQ_EINT0_2412 S3C2410_IRQ(32)
-#define IRQ_EINT1_2412 S3C2410_IRQ(33)
-#define IRQ_EINT2_2412 S3C2410_IRQ(34)
-#define IRQ_EINT3_2412 S3C2410_IRQ(35)
-#define IRQ_EINT4 S3C2410_IRQ(36) /* 52 */
-#define IRQ_EINT5 S3C2410_IRQ(37)
-#define IRQ_EINT6 S3C2410_IRQ(38)
-#define IRQ_EINT7 S3C2410_IRQ(39)
-#define IRQ_EINT8 S3C2410_IRQ(40)
-#define IRQ_EINT9 S3C2410_IRQ(41)
-#define IRQ_EINT10 S3C2410_IRQ(42)
-#define IRQ_EINT11 S3C2410_IRQ(43)
-#define IRQ_EINT12 S3C2410_IRQ(44)
-#define IRQ_EINT13 S3C2410_IRQ(45)
-#define IRQ_EINT14 S3C2410_IRQ(46)
-#define IRQ_EINT15 S3C2410_IRQ(47)
-#define IRQ_EINT16 S3C2410_IRQ(48)
-#define IRQ_EINT17 S3C2410_IRQ(49)
-#define IRQ_EINT18 S3C2410_IRQ(50)
-#define IRQ_EINT19 S3C2410_IRQ(51)
-#define IRQ_EINT20 S3C2410_IRQ(52) /* 68 */
-#define IRQ_EINT21 S3C2410_IRQ(53)
-#define IRQ_EINT22 S3C2410_IRQ(54)
-#define IRQ_EINT23 S3C2410_IRQ(55)
-
-#define IRQ_EINT_BIT(x) ((x) - IRQ_EINT4 + 4)
-#define IRQ_EINT(x) (((x) >= 4) ? (IRQ_EINT4 + (x) - 4) : (IRQ_EINT0 + (x)))
-
-#define IRQ_LCD_FIFO S3C2410_IRQ(56)
-#define IRQ_LCD_FRAME S3C2410_IRQ(57)
-
-/* IRQs for the interal UARTs, and ADC
- * these need to be ordered in number of appearance in the
- * SUBSRC mask register
-*/
-
-#define S3C2410_IRQSUB(x) S3C2410_IRQ((x)+58)
-
-#define IRQ_S3CUART_RX0 S3C2410_IRQSUB(0) /* 74 */
-#define IRQ_S3CUART_TX0 S3C2410_IRQSUB(1)
-#define IRQ_S3CUART_ERR0 S3C2410_IRQSUB(2)
-
-#define IRQ_S3CUART_RX1 S3C2410_IRQSUB(3) /* 77 */
-#define IRQ_S3CUART_TX1 S3C2410_IRQSUB(4)
-#define IRQ_S3CUART_ERR1 S3C2410_IRQSUB(5)
-
-#define IRQ_S3CUART_RX2 S3C2410_IRQSUB(6) /* 80 */
-#define IRQ_S3CUART_TX2 S3C2410_IRQSUB(7)
-#define IRQ_S3CUART_ERR2 S3C2410_IRQSUB(8)
-
-#define IRQ_TC S3C2410_IRQSUB(9)
-#define IRQ_ADC S3C2410_IRQSUB(10)
-
-/* extra irqs for s3c2412 */
-
-#define IRQ_S3C2412_CFSDI S3C2410_IRQ(21)
-
-#define IRQ_S3C2412_SDI S3C2410_IRQSUB(13)
-#define IRQ_S3C2412_CF S3C2410_IRQSUB(14)
-
-
-#define IRQ_S3C2416_EINT8t15 S3C2410_IRQ(5)
-#define IRQ_S3C2416_DMA S3C2410_IRQ(17)
-#define IRQ_S3C2416_UART3 S3C2410_IRQ(18)
-#define IRQ_S3C2416_SDI1 S3C2410_IRQ(20)
-#define IRQ_S3C2416_SDI0 S3C2410_IRQ(21)
-
-#define IRQ_S3C2416_LCD2 S3C2410_IRQSUB(15)
-#define IRQ_S3C2416_LCD3 S3C2410_IRQSUB(16)
-#define IRQ_S3C2416_LCD4 S3C2410_IRQSUB(17)
-#define IRQ_S3C2416_DMA0 S3C2410_IRQSUB(18)
-#define IRQ_S3C2416_DMA1 S3C2410_IRQSUB(19)
-#define IRQ_S3C2416_DMA2 S3C2410_IRQSUB(20)
-#define IRQ_S3C2416_DMA3 S3C2410_IRQSUB(21)
-#define IRQ_S3C2416_DMA4 S3C2410_IRQSUB(22)
-#define IRQ_S3C2416_DMA5 S3C2410_IRQSUB(23)
-#define IRQ_S32416_WDT S3C2410_IRQSUB(27)
-#define IRQ_S32416_AC97 S3C2410_IRQSUB(28)
-
-/* second interrupt-register of s3c2416/s3c2450 */
-
-#define S3C2416_IRQ(x) S3C2410_IRQ((x) + 58 + 29)
-#define IRQ_S3C2416_2D S3C2416_IRQ(0)
-#define IRQ_S3C2416_IIC1 S3C2416_IRQ(1)
-#define IRQ_S3C2416_RESERVED2 S3C2416_IRQ(2)
-#define IRQ_S3C2416_RESERVED3 S3C2416_IRQ(3)
-#define IRQ_S3C2416_PCM0 S3C2416_IRQ(4)
-#define IRQ_S3C2416_PCM1 S3C2416_IRQ(5)
-#define IRQ_S3C2416_I2S0 S3C2416_IRQ(6)
-#define IRQ_S3C2416_I2S1 S3C2416_IRQ(7)
-
-/* extra irqs for s3c2440 */
-
-#define IRQ_S3C2440_CAM_C S3C2410_IRQSUB(11) /* S3C2443 too */
-#define IRQ_S3C2440_CAM_P S3C2410_IRQSUB(12) /* S3C2443 too */
-#define IRQ_S3C2440_WDT S3C2410_IRQSUB(13)
-#define IRQ_S3C2440_AC97 S3C2410_IRQSUB(14)
-
-/* irqs for s3c2443 */
-
-#define IRQ_S3C2443_DMA S3C2410_IRQ(17) /* IRQ_DMA1 */
-#define IRQ_S3C2443_UART3 S3C2410_IRQ(18) /* IRQ_DMA2 */
-#define IRQ_S3C2443_CFCON S3C2410_IRQ(19) /* IRQ_DMA3 */
-#define IRQ_S3C2443_HSMMC S3C2410_IRQ(20) /* IRQ_SDI */
-#define IRQ_S3C2443_NAND S3C2410_IRQ(24) /* reserved */
-
-#define IRQ_S3C2416_HSMMC0 S3C2410_IRQ(21) /* S3C2416/S3C2450 */
-
-#define IRQ_HSMMC0 IRQ_S3C2416_HSMMC0
-#define IRQ_HSMMC1 IRQ_S3C2443_HSMMC
-
-#define IRQ_S3C2443_LCD1 S3C2410_IRQSUB(14)
-#define IRQ_S3C2443_LCD2 S3C2410_IRQSUB(15)
-#define IRQ_S3C2443_LCD3 S3C2410_IRQSUB(16)
-#define IRQ_S3C2443_LCD4 S3C2410_IRQSUB(17)
-
-#define IRQ_S3C2443_DMA0 S3C2410_IRQSUB(18)
-#define IRQ_S3C2443_DMA1 S3C2410_IRQSUB(19)
-#define IRQ_S3C2443_DMA2 S3C2410_IRQSUB(20)
-#define IRQ_S3C2443_DMA3 S3C2410_IRQSUB(21)
-#define IRQ_S3C2443_DMA4 S3C2410_IRQSUB(22)
-#define IRQ_S3C2443_DMA5 S3C2410_IRQSUB(23)
-
-/* UART3 */
-#define IRQ_S3C2443_RX3 S3C2410_IRQSUB(24)
-#define IRQ_S3C2443_TX3 S3C2410_IRQSUB(25)
-#define IRQ_S3C2443_ERR3 S3C2410_IRQSUB(26)
-
-#define IRQ_S3C2443_WDT S3C2410_IRQSUB(27)
-#define IRQ_S3C2443_AC97 S3C2410_IRQSUB(28)
-
-#if defined(CONFIG_CPU_S3C2416)
-#define NR_IRQS (IRQ_S3C2416_I2S1 + 1)
-#else
-#define NR_IRQS (IRQ_S3C2443_AC97 + 1)
-#endif
-
-/* compatibility define. */
-#define IRQ_UART3 IRQ_S3C2443_UART3
-#define IRQ_S3CUART_RX3 IRQ_S3C2443_RX3
-#define IRQ_S3CUART_TX3 IRQ_S3C2443_TX3
-#define IRQ_S3CUART_ERR3 IRQ_S3C2443_ERR3
-
-#define IRQ_LCD_VSYNC IRQ_S3C2443_LCD3
-#define IRQ_LCD_SYSTEM IRQ_S3C2443_LCD2
-
-#ifdef CONFIG_CPU_S3C2440
-#define IRQ_S3C244X_AC97 IRQ_S3C2440_AC97
-#else
-#define IRQ_S3C244X_AC97 IRQ_S3C2443_AC97
-#endif
-
-/* Our FIQs are routable from IRQ_EINT0 to IRQ_ADCPARENT */
-#define FIQ_START IRQ_EINT0
-
-#endif /* __ASM_ARCH_IRQ_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/* linux/arch/arm/mach-s3c64xx/include/mach/irqs.h
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- * Ben Dooks <ben@simtec.co.uk>
- * http://armlinux.simtec.co.uk/
- *
- * S3C64XX - IRQ support
- */
-
-#ifndef __ASM_MACH_S3C64XX_IRQS_H
-#define __ASM_MACH_S3C64XX_IRQS_H __FILE__
-
-/* we keep the first set of CPU IRQs out of the range of
- * the ISA space, so that the PC104 has them to itself
- * and we don't end up having to do horrible things to the
- * standard ISA drivers....
- *
- * note, since we're using the VICs, our start must be a
- * mulitple of 32 to allow the common code to work
- */
-
-#define S3C_IRQ_OFFSET (32)
-
-#define S3C_IRQ(x) ((x) + S3C_IRQ_OFFSET)
-
-#define IRQ_VIC0_BASE S3C_IRQ(0)
-#define IRQ_VIC1_BASE S3C_IRQ(32)
-
-/* VIC based IRQs */
-
-#define S3C64XX_IRQ_VIC0(x) (IRQ_VIC0_BASE + (x))
-#define S3C64XX_IRQ_VIC1(x) (IRQ_VIC1_BASE + (x))
-
-/* VIC0 */
-
-#define IRQ_EINT0_3 S3C64XX_IRQ_VIC0(0)
-#define IRQ_EINT4_11 S3C64XX_IRQ_VIC0(1)
-#define IRQ_RTC_TIC S3C64XX_IRQ_VIC0(2)
-#define IRQ_CAMIF_C S3C64XX_IRQ_VIC0(3)
-#define IRQ_CAMIF_P S3C64XX_IRQ_VIC0(4)
-#define IRQ_CAMIF_MC S3C64XX_IRQ_VIC0(5)
-#define IRQ_S3C6410_IIC1 S3C64XX_IRQ_VIC0(5)
-#define IRQ_S3C6410_IIS S3C64XX_IRQ_VIC0(6)
-#define IRQ_S3C6400_CAMIF_MP S3C64XX_IRQ_VIC0(6)
-#define IRQ_CAMIF_WE_C S3C64XX_IRQ_VIC0(7)
-#define IRQ_S3C6410_G3D S3C64XX_IRQ_VIC0(8)
-#define IRQ_S3C6400_CAMIF_WE_P S3C64XX_IRQ_VIC0(8)
-#define IRQ_POST0 S3C64XX_IRQ_VIC0(9)
-#define IRQ_ROTATOR S3C64XX_IRQ_VIC0(10)
-#define IRQ_2D S3C64XX_IRQ_VIC0(11)
-#define IRQ_TVENC S3C64XX_IRQ_VIC0(12)
-#define IRQ_SCALER S3C64XX_IRQ_VIC0(13)
-#define IRQ_BATF S3C64XX_IRQ_VIC0(14)
-#define IRQ_JPEG S3C64XX_IRQ_VIC0(15)
-#define IRQ_MFC S3C64XX_IRQ_VIC0(16)
-#define IRQ_SDMA0 S3C64XX_IRQ_VIC0(17)
-#define IRQ_SDMA1 S3C64XX_IRQ_VIC0(18)
-#define IRQ_ARM_DMAERR S3C64XX_IRQ_VIC0(19)
-#define IRQ_ARM_DMA S3C64XX_IRQ_VIC0(20)
-#define IRQ_ARM_DMAS S3C64XX_IRQ_VIC0(21)
-#define IRQ_KEYPAD S3C64XX_IRQ_VIC0(22)
-#define IRQ_TIMER0_VIC S3C64XX_IRQ_VIC0(23)
-#define IRQ_TIMER1_VIC S3C64XX_IRQ_VIC0(24)
-#define IRQ_TIMER2_VIC S3C64XX_IRQ_VIC0(25)
-#define IRQ_WDT S3C64XX_IRQ_VIC0(26)
-#define IRQ_TIMER3_VIC S3C64XX_IRQ_VIC0(27)
-#define IRQ_TIMER4_VIC S3C64XX_IRQ_VIC0(28)
-#define IRQ_LCD_FIFO S3C64XX_IRQ_VIC0(29)
-#define IRQ_LCD_VSYNC S3C64XX_IRQ_VIC0(30)
-#define IRQ_LCD_SYSTEM S3C64XX_IRQ_VIC0(31)
-
-/* VIC1 */
-
-#define IRQ_EINT12_19 S3C64XX_IRQ_VIC1(0)
-#define IRQ_EINT20_27 S3C64XX_IRQ_VIC1(1)
-#define IRQ_PCM0 S3C64XX_IRQ_VIC1(2)
-#define IRQ_PCM1 S3C64XX_IRQ_VIC1(3)
-#define IRQ_AC97 S3C64XX_IRQ_VIC1(4)
-#define IRQ_UART0 S3C64XX_IRQ_VIC1(5)
-#define IRQ_UART1 S3C64XX_IRQ_VIC1(6)
-#define IRQ_UART2 S3C64XX_IRQ_VIC1(7)
-#define IRQ_UART3 S3C64XX_IRQ_VIC1(8)
-#define IRQ_DMA0 S3C64XX_IRQ_VIC1(9)
-#define IRQ_DMA1 S3C64XX_IRQ_VIC1(10)
-#define IRQ_ONENAND0 S3C64XX_IRQ_VIC1(11)
-#define IRQ_ONENAND1 S3C64XX_IRQ_VIC1(12)
-#define IRQ_NFC S3C64XX_IRQ_VIC1(13)
-#define IRQ_CFCON S3C64XX_IRQ_VIC1(14)
-#define IRQ_USBH S3C64XX_IRQ_VIC1(15)
-#define IRQ_SPI0 S3C64XX_IRQ_VIC1(16)
-#define IRQ_SPI1 S3C64XX_IRQ_VIC1(17)
-#define IRQ_IIC S3C64XX_IRQ_VIC1(18)
-#define IRQ_HSItx S3C64XX_IRQ_VIC1(19)
-#define IRQ_HSIrx S3C64XX_IRQ_VIC1(20)
-#define IRQ_RESERVED S3C64XX_IRQ_VIC1(21)
-#define IRQ_MSM S3C64XX_IRQ_VIC1(22)
-#define IRQ_HOSTIF S3C64XX_IRQ_VIC1(23)
-#define IRQ_HSMMC0 S3C64XX_IRQ_VIC1(24)
-#define IRQ_HSMMC1 S3C64XX_IRQ_VIC1(25)
-#define IRQ_HSMMC2 IRQ_SPI1 /* shared with SPI1 */
-#define IRQ_OTG S3C64XX_IRQ_VIC1(26)
-#define IRQ_IRDA S3C64XX_IRQ_VIC1(27)
-#define IRQ_RTC_ALARM S3C64XX_IRQ_VIC1(28)
-#define IRQ_SEC S3C64XX_IRQ_VIC1(29)
-#define IRQ_PENDN S3C64XX_IRQ_VIC1(30)
-#define IRQ_TC IRQ_PENDN
-#define IRQ_ADC S3C64XX_IRQ_VIC1(31)
-
-/* compatibility for device defines */
-
-#define IRQ_IIC1 IRQ_S3C6410_IIC1
-
-/* Since the IRQ_EINT(x) are a linear mapping on current s3c64xx series
- * we just defined them as an IRQ_EINT(x) macro from S3C_IRQ_EINT_BASE
- * which we place after the pair of VICs. */
-
-#define S3C_IRQ_EINT_BASE S3C_IRQ(64+5)
-
-#define S3C_EINT(x) ((x) + S3C_IRQ_EINT_BASE)
-#define IRQ_EINT(x) S3C_EINT(x)
-#define IRQ_EINT_BIT(x) ((x) - S3C_EINT(0))
-
-/* Next the external interrupt groups. These are similar to the IRQ_EINT(x)
- * that they are sourced from the GPIO pins but with a different scheme for
- * priority and source indication.
- *
- * The IRQ_EINT(x) can be thought of as 'group 0' of the available GPIO
- * interrupts, but for historical reasons they are kept apart from these
- * next interrupts.
- *
- * Use IRQ_EINT_GROUP(group, offset) to get the number for use in the
- * machine specific support files.
- */
-
-#define IRQ_EINT_GROUP1_NR (15)
-#define IRQ_EINT_GROUP2_NR (8)
-#define IRQ_EINT_GROUP3_NR (5)
-#define IRQ_EINT_GROUP4_NR (14)
-#define IRQ_EINT_GROUP5_NR (7)
-#define IRQ_EINT_GROUP6_NR (10)
-#define IRQ_EINT_GROUP7_NR (16)
-#define IRQ_EINT_GROUP8_NR (15)
-#define IRQ_EINT_GROUP9_NR (9)
-
-#define IRQ_EINT_GROUP_BASE S3C_EINT(28)
-#define IRQ_EINT_GROUP1_BASE (IRQ_EINT_GROUP_BASE + 0x00)
-#define IRQ_EINT_GROUP2_BASE (IRQ_EINT_GROUP1_BASE + IRQ_EINT_GROUP1_NR)
-#define IRQ_EINT_GROUP3_BASE (IRQ_EINT_GROUP2_BASE + IRQ_EINT_GROUP2_NR)
-#define IRQ_EINT_GROUP4_BASE (IRQ_EINT_GROUP3_BASE + IRQ_EINT_GROUP3_NR)
-#define IRQ_EINT_GROUP5_BASE (IRQ_EINT_GROUP4_BASE + IRQ_EINT_GROUP4_NR)
-#define IRQ_EINT_GROUP6_BASE (IRQ_EINT_GROUP5_BASE + IRQ_EINT_GROUP5_NR)
-#define IRQ_EINT_GROUP7_BASE (IRQ_EINT_GROUP6_BASE + IRQ_EINT_GROUP6_NR)
-#define IRQ_EINT_GROUP8_BASE (IRQ_EINT_GROUP7_BASE + IRQ_EINT_GROUP7_NR)
-#define IRQ_EINT_GROUP9_BASE (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR)
-
-#define IRQ_EINT_GROUP(group, no) (IRQ_EINT_GROUP##group##_BASE + (no))
-
-/* Some boards have their own IRQs behind this */
-#define IRQ_BOARD_START (IRQ_EINT_GROUP9_BASE + IRQ_EINT_GROUP9_NR + 1)
-
-/* Set the default nr_irqs, boards can override if necessary */
-#define S3C64XX_NR_IRQS IRQ_BOARD_START
-
-/* Compatibility */
-
-#define IRQ_ONENAND IRQ_ONENAND0
-#define IRQ_I2S0 IRQ_S3C6410_IIS
-
-#endif /* __ASM_MACH_S3C64XX_IRQS_H */
-
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-
-#ifdef CONFIG_ARCH_S3C24XX
-#include "irqs-s3c24xx.h"
-#endif
-
-#ifdef CONFIG_ARCH_S3C64XX
-#include "irqs-s3c64xx.h"
-#endif
#include <asm/exception.h>
#include <asm/mach/irq.h>
-#include <mach/irqs.h>
+#include "irqs.h"
#include "regs-irq.h"
#include "regs-gpio.h"
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2003-2005 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ */
+
+
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H __FILE__
+
+/* we keep the first set of CPU IRQs out of the range of
+ * the ISA space, so that the PC104 has them to itself
+ * and we don't end up having to do horrible things to the
+ * standard ISA drivers....
+ */
+
+#define S3C2410_CPUIRQ_OFFSET (16)
+
+#define S3C2410_IRQ(x) ((x) + S3C2410_CPUIRQ_OFFSET)
+
+/* main cpu interrupts */
+#define IRQ_EINT0 S3C2410_IRQ(0) /* 16 */
+#define IRQ_EINT1 S3C2410_IRQ(1)
+#define IRQ_EINT2 S3C2410_IRQ(2)
+#define IRQ_EINT3 S3C2410_IRQ(3)
+#define IRQ_EINT4t7 S3C2410_IRQ(4) /* 20 */
+#define IRQ_EINT8t23 S3C2410_IRQ(5)
+#define IRQ_RESERVED6 S3C2410_IRQ(6) /* for s3c2410 */
+#define IRQ_CAM S3C2410_IRQ(6) /* for s3c2440,s3c2443 */
+#define IRQ_BATT_FLT S3C2410_IRQ(7)
+#define IRQ_TICK S3C2410_IRQ(8) /* 24 */
+#define IRQ_WDT S3C2410_IRQ(9) /* WDT/AC97 for s3c2443 */
+#define IRQ_TIMER0 S3C2410_IRQ(10)
+#define IRQ_TIMER1 S3C2410_IRQ(11)
+#define IRQ_TIMER2 S3C2410_IRQ(12)
+#define IRQ_TIMER3 S3C2410_IRQ(13)
+#define IRQ_TIMER4 S3C2410_IRQ(14)
+#define IRQ_UART2 S3C2410_IRQ(15)
+#define IRQ_LCD S3C2410_IRQ(16) /* 32 */
+#define IRQ_DMA0 S3C2410_IRQ(17) /* IRQ_DMA for s3c2443 */
+#define IRQ_DMA1 S3C2410_IRQ(18)
+#define IRQ_DMA2 S3C2410_IRQ(19)
+#define IRQ_DMA3 S3C2410_IRQ(20)
+#define IRQ_SDI S3C2410_IRQ(21)
+#define IRQ_SPI0 S3C2410_IRQ(22)
+#define IRQ_UART1 S3C2410_IRQ(23)
+#define IRQ_RESERVED24 S3C2410_IRQ(24) /* 40 */
+#define IRQ_NFCON S3C2410_IRQ(24) /* for s3c2440 */
+#define IRQ_USBD S3C2410_IRQ(25)
+#define IRQ_USBH S3C2410_IRQ(26)
+#define IRQ_IIC S3C2410_IRQ(27)
+#define IRQ_UART0 S3C2410_IRQ(28) /* 44 */
+#define IRQ_SPI1 S3C2410_IRQ(29)
+#define IRQ_RTC S3C2410_IRQ(30)
+#define IRQ_ADCPARENT S3C2410_IRQ(31)
+
+/* interrupts generated from the external interrupts sources */
+#define IRQ_EINT0_2412 S3C2410_IRQ(32)
+#define IRQ_EINT1_2412 S3C2410_IRQ(33)
+#define IRQ_EINT2_2412 S3C2410_IRQ(34)
+#define IRQ_EINT3_2412 S3C2410_IRQ(35)
+#define IRQ_EINT4 S3C2410_IRQ(36) /* 52 */
+#define IRQ_EINT5 S3C2410_IRQ(37)
+#define IRQ_EINT6 S3C2410_IRQ(38)
+#define IRQ_EINT7 S3C2410_IRQ(39)
+#define IRQ_EINT8 S3C2410_IRQ(40)
+#define IRQ_EINT9 S3C2410_IRQ(41)
+#define IRQ_EINT10 S3C2410_IRQ(42)
+#define IRQ_EINT11 S3C2410_IRQ(43)
+#define IRQ_EINT12 S3C2410_IRQ(44)
+#define IRQ_EINT13 S3C2410_IRQ(45)
+#define IRQ_EINT14 S3C2410_IRQ(46)
+#define IRQ_EINT15 S3C2410_IRQ(47)
+#define IRQ_EINT16 S3C2410_IRQ(48)
+#define IRQ_EINT17 S3C2410_IRQ(49)
+#define IRQ_EINT18 S3C2410_IRQ(50)
+#define IRQ_EINT19 S3C2410_IRQ(51)
+#define IRQ_EINT20 S3C2410_IRQ(52) /* 68 */
+#define IRQ_EINT21 S3C2410_IRQ(53)
+#define IRQ_EINT22 S3C2410_IRQ(54)
+#define IRQ_EINT23 S3C2410_IRQ(55)
+
+#define IRQ_EINT_BIT(x) ((x) - IRQ_EINT4 + 4)
+#define IRQ_EINT(x) (((x) >= 4) ? (IRQ_EINT4 + (x) - 4) : (IRQ_EINT0 + (x)))
+
+#define IRQ_LCD_FIFO S3C2410_IRQ(56)
+#define IRQ_LCD_FRAME S3C2410_IRQ(57)
+
+/* IRQs for the interal UARTs, and ADC
+ * these need to be ordered in number of appearance in the
+ * SUBSRC mask register
+*/
+
+#define S3C2410_IRQSUB(x) S3C2410_IRQ((x)+58)
+
+#define IRQ_S3CUART_RX0 S3C2410_IRQSUB(0) /* 74 */
+#define IRQ_S3CUART_TX0 S3C2410_IRQSUB(1)
+#define IRQ_S3CUART_ERR0 S3C2410_IRQSUB(2)
+
+#define IRQ_S3CUART_RX1 S3C2410_IRQSUB(3) /* 77 */
+#define IRQ_S3CUART_TX1 S3C2410_IRQSUB(4)
+#define IRQ_S3CUART_ERR1 S3C2410_IRQSUB(5)
+
+#define IRQ_S3CUART_RX2 S3C2410_IRQSUB(6) /* 80 */
+#define IRQ_S3CUART_TX2 S3C2410_IRQSUB(7)
+#define IRQ_S3CUART_ERR2 S3C2410_IRQSUB(8)
+
+#define IRQ_TC S3C2410_IRQSUB(9)
+#define IRQ_ADC S3C2410_IRQSUB(10)
+
+#define NR_IRQS_S3C2410 (S3C2410_IRQSUB(10) + 1)
+
+/* extra irqs for s3c2412 */
+
+#define IRQ_S3C2412_CFSDI S3C2410_IRQ(21)
+
+#define IRQ_S3C2412_SDI S3C2410_IRQSUB(13)
+#define IRQ_S3C2412_CF S3C2410_IRQSUB(14)
+
+#define NR_IRQS_S3C2412 (S3C2410_IRQSUB(14) + 1)
+
+#define IRQ_S3C2416_EINT8t15 S3C2410_IRQ(5)
+#define IRQ_S3C2416_DMA S3C2410_IRQ(17)
+#define IRQ_S3C2416_UART3 S3C2410_IRQ(18)
+#define IRQ_S3C2416_SDI1 S3C2410_IRQ(20)
+#define IRQ_S3C2416_SDI0 S3C2410_IRQ(21)
+
+#define IRQ_S3C2416_LCD2 S3C2410_IRQSUB(15)
+#define IRQ_S3C2416_LCD3 S3C2410_IRQSUB(16)
+#define IRQ_S3C2416_LCD4 S3C2410_IRQSUB(17)
+#define IRQ_S3C2416_DMA0 S3C2410_IRQSUB(18)
+#define IRQ_S3C2416_DMA1 S3C2410_IRQSUB(19)
+#define IRQ_S3C2416_DMA2 S3C2410_IRQSUB(20)
+#define IRQ_S3C2416_DMA3 S3C2410_IRQSUB(21)
+#define IRQ_S3C2416_DMA4 S3C2410_IRQSUB(22)
+#define IRQ_S3C2416_DMA5 S3C2410_IRQSUB(23)
+#define IRQ_S32416_WDT S3C2410_IRQSUB(27)
+#define IRQ_S32416_AC97 S3C2410_IRQSUB(28)
+
+/* second interrupt-register of s3c2416/s3c2450 */
+
+#define S3C2416_IRQ(x) S3C2410_IRQ((x) + 58 + 29)
+#define IRQ_S3C2416_2D S3C2416_IRQ(0)
+#define IRQ_S3C2416_IIC1 S3C2416_IRQ(1)
+#define IRQ_S3C2416_RESERVED2 S3C2416_IRQ(2)
+#define IRQ_S3C2416_RESERVED3 S3C2416_IRQ(3)
+#define IRQ_S3C2416_PCM0 S3C2416_IRQ(4)
+#define IRQ_S3C2416_PCM1 S3C2416_IRQ(5)
+#define IRQ_S3C2416_I2S0 S3C2416_IRQ(6)
+#define IRQ_S3C2416_I2S1 S3C2416_IRQ(7)
+
+#define NR_IRQS_S3C2416 (S3C2416_IRQ(7) + 1)
+
+/* extra irqs for s3c2440/s3c2442 */
+
+#define IRQ_S3C2440_CAM_C S3C2410_IRQSUB(11) /* S3C2443 too */
+#define IRQ_S3C2440_CAM_P S3C2410_IRQSUB(12) /* S3C2443 too */
+
+#define NR_IRQS_S3C2442 (S3C2410_IRQSUB(12) + 1)
+
+#define IRQ_S3C2440_WDT S3C2410_IRQSUB(13)
+#define IRQ_S3C2440_AC97 S3C2410_IRQSUB(14)
+
+#define NR_IRQS_S3C2440 (S3C2410_IRQSUB(14) + 1)
+
+/* irqs for s3c2443 */
+
+#define IRQ_S3C2443_DMA S3C2410_IRQ(17) /* IRQ_DMA1 */
+#define IRQ_S3C2443_UART3 S3C2410_IRQ(18) /* IRQ_DMA2 */
+#define IRQ_S3C2443_CFCON S3C2410_IRQ(19) /* IRQ_DMA3 */
+#define IRQ_S3C2443_HSMMC S3C2410_IRQ(20) /* IRQ_SDI */
+#define IRQ_S3C2443_NAND S3C2410_IRQ(24) /* reserved */
+
+#define IRQ_S3C2416_HSMMC0 S3C2410_IRQ(21) /* S3C2416/S3C2450 */
+
+#define IRQ_HSMMC0 IRQ_S3C2416_HSMMC0
+#define IRQ_HSMMC1 IRQ_S3C2443_HSMMC
+
+#define IRQ_S3C2443_LCD1 S3C2410_IRQSUB(14)
+#define IRQ_S3C2443_LCD2 S3C2410_IRQSUB(15)
+#define IRQ_S3C2443_LCD3 S3C2410_IRQSUB(16)
+#define IRQ_S3C2443_LCD4 S3C2410_IRQSUB(17)
+
+#define IRQ_S3C2443_DMA0 S3C2410_IRQSUB(18)
+#define IRQ_S3C2443_DMA1 S3C2410_IRQSUB(19)
+#define IRQ_S3C2443_DMA2 S3C2410_IRQSUB(20)
+#define IRQ_S3C2443_DMA3 S3C2410_IRQSUB(21)
+#define IRQ_S3C2443_DMA4 S3C2410_IRQSUB(22)
+#define IRQ_S3C2443_DMA5 S3C2410_IRQSUB(23)
+
+/* UART3 */
+#define IRQ_S3C2443_RX3 S3C2410_IRQSUB(24)
+#define IRQ_S3C2443_TX3 S3C2410_IRQSUB(25)
+#define IRQ_S3C2443_ERR3 S3C2410_IRQSUB(26)
+
+#define IRQ_S3C2443_WDT S3C2410_IRQSUB(27)
+#define IRQ_S3C2443_AC97 S3C2410_IRQSUB(28)
+
+#define NR_IRQS_S3C2443 (S3C2410_IRQSUB(28) + 1)
+
+/* compatibility define. */
+#define IRQ_UART3 IRQ_S3C2443_UART3
+#define IRQ_S3CUART_RX3 IRQ_S3C2443_RX3
+#define IRQ_S3CUART_TX3 IRQ_S3C2443_TX3
+#define IRQ_S3CUART_ERR3 IRQ_S3C2443_ERR3
+
+#define IRQ_LCD_VSYNC IRQ_S3C2443_LCD3
+#define IRQ_LCD_SYSTEM IRQ_S3C2443_LCD2
+
+#ifdef CONFIG_CPU_S3C2440
+#define IRQ_S3C244X_AC97 IRQ_S3C2440_AC97
+#else
+#define IRQ_S3C244X_AC97 IRQ_S3C2443_AC97
+#endif
+
+/* Our FIQs are routable from IRQ_EINT0 to IRQ_ADCPARENT */
+#define FIQ_START IRQ_EINT0
+
+#endif /* __ASM_ARCH_IRQ_H */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 */
+/* linux/arch/arm/mach-s3c64xx/include/mach/irqs.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * S3C64XX - IRQ support
+ */
+
+#ifndef __ASM_MACH_S3C64XX_IRQS_H
+#define __ASM_MACH_S3C64XX_IRQS_H __FILE__
+
+/* we keep the first set of CPU IRQs out of the range of
+ * the ISA space, so that the PC104 has them to itself
+ * and we don't end up having to do horrible things to the
+ * standard ISA drivers....
+ *
+ * note, since we're using the VICs, our start must be a
+ * mulitple of 32 to allow the common code to work
+ */
+
+#define S3C_IRQ_OFFSET (32)
+
+#define S3C_IRQ(x) ((x) + S3C_IRQ_OFFSET)
+
+#define IRQ_VIC0_BASE S3C_IRQ(0)
+#define IRQ_VIC1_BASE S3C_IRQ(32)
+
+/* VIC based IRQs */
+
+#define S3C64XX_IRQ_VIC0(x) (IRQ_VIC0_BASE + (x))
+#define S3C64XX_IRQ_VIC1(x) (IRQ_VIC1_BASE + (x))
+
+/* VIC0 */
+
+#define IRQ_EINT0_3 S3C64XX_IRQ_VIC0(0)
+#define IRQ_EINT4_11 S3C64XX_IRQ_VIC0(1)
+#define IRQ_RTC_TIC S3C64XX_IRQ_VIC0(2)
+#define IRQ_CAMIF_C S3C64XX_IRQ_VIC0(3)
+#define IRQ_CAMIF_P S3C64XX_IRQ_VIC0(4)
+#define IRQ_CAMIF_MC S3C64XX_IRQ_VIC0(5)
+#define IRQ_S3C6410_IIC1 S3C64XX_IRQ_VIC0(5)
+#define IRQ_S3C6410_IIS S3C64XX_IRQ_VIC0(6)
+#define IRQ_S3C6400_CAMIF_MP S3C64XX_IRQ_VIC0(6)
+#define IRQ_CAMIF_WE_C S3C64XX_IRQ_VIC0(7)
+#define IRQ_S3C6410_G3D S3C64XX_IRQ_VIC0(8)
+#define IRQ_S3C6400_CAMIF_WE_P S3C64XX_IRQ_VIC0(8)
+#define IRQ_POST0 S3C64XX_IRQ_VIC0(9)
+#define IRQ_ROTATOR S3C64XX_IRQ_VIC0(10)
+#define IRQ_2D S3C64XX_IRQ_VIC0(11)
+#define IRQ_TVENC S3C64XX_IRQ_VIC0(12)
+#define IRQ_SCALER S3C64XX_IRQ_VIC0(13)
+#define IRQ_BATF S3C64XX_IRQ_VIC0(14)
+#define IRQ_JPEG S3C64XX_IRQ_VIC0(15)
+#define IRQ_MFC S3C64XX_IRQ_VIC0(16)
+#define IRQ_SDMA0 S3C64XX_IRQ_VIC0(17)
+#define IRQ_SDMA1 S3C64XX_IRQ_VIC0(18)
+#define IRQ_ARM_DMAERR S3C64XX_IRQ_VIC0(19)
+#define IRQ_ARM_DMA S3C64XX_IRQ_VIC0(20)
+#define IRQ_ARM_DMAS S3C64XX_IRQ_VIC0(21)
+#define IRQ_KEYPAD S3C64XX_IRQ_VIC0(22)
+#define IRQ_TIMER0_VIC S3C64XX_IRQ_VIC0(23)
+#define IRQ_TIMER1_VIC S3C64XX_IRQ_VIC0(24)
+#define IRQ_TIMER2_VIC S3C64XX_IRQ_VIC0(25)
+#define IRQ_WDT S3C64XX_IRQ_VIC0(26)
+#define IRQ_TIMER3_VIC S3C64XX_IRQ_VIC0(27)
+#define IRQ_TIMER4_VIC S3C64XX_IRQ_VIC0(28)
+#define IRQ_LCD_FIFO S3C64XX_IRQ_VIC0(29)
+#define IRQ_LCD_VSYNC S3C64XX_IRQ_VIC0(30)
+#define IRQ_LCD_SYSTEM S3C64XX_IRQ_VIC0(31)
+
+/* VIC1 */
+
+#define IRQ_EINT12_19 S3C64XX_IRQ_VIC1(0)
+#define IRQ_EINT20_27 S3C64XX_IRQ_VIC1(1)
+#define IRQ_PCM0 S3C64XX_IRQ_VIC1(2)
+#define IRQ_PCM1 S3C64XX_IRQ_VIC1(3)
+#define IRQ_AC97 S3C64XX_IRQ_VIC1(4)
+#define IRQ_UART0 S3C64XX_IRQ_VIC1(5)
+#define IRQ_UART1 S3C64XX_IRQ_VIC1(6)
+#define IRQ_UART2 S3C64XX_IRQ_VIC1(7)
+#define IRQ_UART3 S3C64XX_IRQ_VIC1(8)
+#define IRQ_DMA0 S3C64XX_IRQ_VIC1(9)
+#define IRQ_DMA1 S3C64XX_IRQ_VIC1(10)
+#define IRQ_ONENAND0 S3C64XX_IRQ_VIC1(11)
+#define IRQ_ONENAND1 S3C64XX_IRQ_VIC1(12)
+#define IRQ_NFC S3C64XX_IRQ_VIC1(13)
+#define IRQ_CFCON S3C64XX_IRQ_VIC1(14)
+#define IRQ_USBH S3C64XX_IRQ_VIC1(15)
+#define IRQ_SPI0 S3C64XX_IRQ_VIC1(16)
+#define IRQ_SPI1 S3C64XX_IRQ_VIC1(17)
+#define IRQ_IIC S3C64XX_IRQ_VIC1(18)
+#define IRQ_HSItx S3C64XX_IRQ_VIC1(19)
+#define IRQ_HSIrx S3C64XX_IRQ_VIC1(20)
+#define IRQ_RESERVED S3C64XX_IRQ_VIC1(21)
+#define IRQ_MSM S3C64XX_IRQ_VIC1(22)
+#define IRQ_HOSTIF S3C64XX_IRQ_VIC1(23)
+#define IRQ_HSMMC0 S3C64XX_IRQ_VIC1(24)
+#define IRQ_HSMMC1 S3C64XX_IRQ_VIC1(25)
+#define IRQ_HSMMC2 IRQ_SPI1 /* shared with SPI1 */
+#define IRQ_OTG S3C64XX_IRQ_VIC1(26)
+#define IRQ_IRDA S3C64XX_IRQ_VIC1(27)
+#define IRQ_RTC_ALARM S3C64XX_IRQ_VIC1(28)
+#define IRQ_SEC S3C64XX_IRQ_VIC1(29)
+#define IRQ_PENDN S3C64XX_IRQ_VIC1(30)
+#define IRQ_TC IRQ_PENDN
+#define IRQ_ADC S3C64XX_IRQ_VIC1(31)
+
+/* compatibility for device defines */
+
+#define IRQ_IIC1 IRQ_S3C6410_IIC1
+
+/* Since the IRQ_EINT(x) are a linear mapping on current s3c64xx series
+ * we just defined them as an IRQ_EINT(x) macro from S3C_IRQ_EINT_BASE
+ * which we place after the pair of VICs. */
+
+#define S3C_IRQ_EINT_BASE S3C_IRQ(64+5)
+
+#define S3C_EINT(x) ((x) + S3C_IRQ_EINT_BASE)
+#define IRQ_EINT(x) S3C_EINT(x)
+#define IRQ_EINT_BIT(x) ((x) - S3C_EINT(0))
+
+/* Next the external interrupt groups. These are similar to the IRQ_EINT(x)
+ * that they are sourced from the GPIO pins but with a different scheme for
+ * priority and source indication.
+ *
+ * The IRQ_EINT(x) can be thought of as 'group 0' of the available GPIO
+ * interrupts, but for historical reasons they are kept apart from these
+ * next interrupts.
+ *
+ * Use IRQ_EINT_GROUP(group, offset) to get the number for use in the
+ * machine specific support files.
+ */
+
+#define IRQ_EINT_GROUP1_NR (15)
+#define IRQ_EINT_GROUP2_NR (8)
+#define IRQ_EINT_GROUP3_NR (5)
+#define IRQ_EINT_GROUP4_NR (14)
+#define IRQ_EINT_GROUP5_NR (7)
+#define IRQ_EINT_GROUP6_NR (10)
+#define IRQ_EINT_GROUP7_NR (16)
+#define IRQ_EINT_GROUP8_NR (15)
+#define IRQ_EINT_GROUP9_NR (9)
+
+#define IRQ_EINT_GROUP_BASE S3C_EINT(28)
+#define IRQ_EINT_GROUP1_BASE (IRQ_EINT_GROUP_BASE + 0x00)
+#define IRQ_EINT_GROUP2_BASE (IRQ_EINT_GROUP1_BASE + IRQ_EINT_GROUP1_NR)
+#define IRQ_EINT_GROUP3_BASE (IRQ_EINT_GROUP2_BASE + IRQ_EINT_GROUP2_NR)
+#define IRQ_EINT_GROUP4_BASE (IRQ_EINT_GROUP3_BASE + IRQ_EINT_GROUP3_NR)
+#define IRQ_EINT_GROUP5_BASE (IRQ_EINT_GROUP4_BASE + IRQ_EINT_GROUP4_NR)
+#define IRQ_EINT_GROUP6_BASE (IRQ_EINT_GROUP5_BASE + IRQ_EINT_GROUP5_NR)
+#define IRQ_EINT_GROUP7_BASE (IRQ_EINT_GROUP6_BASE + IRQ_EINT_GROUP6_NR)
+#define IRQ_EINT_GROUP8_BASE (IRQ_EINT_GROUP7_BASE + IRQ_EINT_GROUP7_NR)
+#define IRQ_EINT_GROUP9_BASE (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR)
+
+#define IRQ_EINT_GROUP(group, no) (IRQ_EINT_GROUP##group##_BASE + (no))
+
+/* Some boards have their own IRQs behind this */
+#define IRQ_BOARD_START (IRQ_EINT_GROUP9_BASE + IRQ_EINT_GROUP9_NR + 1)
+
+/* Set the default nr_irqs, boards can override if necessary */
+#define S3C64XX_NR_IRQS IRQ_BOARD_START
+
+/* Compatibility */
+
+#define IRQ_ONENAND IRQ_ONENAND0
+#define IRQ_I2S0 IRQ_S3C6410_IIS
+
+#endif /* __ASM_MACH_S3C64XX_IRQS_H */
+
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifdef CONFIG_ARCH_S3C24XX
+#include "irqs-s3c24xx.h"
+#endif
+
+#ifdef CONFIG_ARCH_S3C64XX
+#include "irqs-s3c64xx.h"
+#endif
MACHINE_START(AML_M5900, "AML_M5900")
.atag_offset = 0x100,
+ .nr_irqs = NR_IRQS_S3C2410,
.map_io = amlm5900_map_io,
+ .nr_irqs = NR_IRQS_S3C2410,
.init_irq = s3c2410_init_irq,
.init_machine = amlm5900_init,
.init_time = amlm5900_init_time,
MACHINE_START(ANUBIS, "Simtec-Anubis")
/* Maintainer: Ben Dooks <ben@simtec.co.uk> */
.atag_offset = 0x100,
+ .nr_irqs = NR_IRQS_S3C2440,
.map_io = anubis_map_io,
.init_machine = anubis_init,
.init_irq = s3c2440_init_irq,
#include "devs.h"
#include "cpu.h"
-#include <mach/irqs.h>
+#include "irqs.h"
#include "regs-gpio.h"
#include "gpio-samsung.h"
MACHINE_START(AT2440EVB, "AT2440EVB")
.atag_offset = 0x100,
+ .nr_irqs = NR_IRQS_S3C2440,
.map_io = at2440evb_map_io,
.init_machine = at2440evb_init,
.init_irq = s3c2440_init_irq,
MACHINE_START(BAST, "Simtec-BAST")
/* Maintainer: Ben Dooks <ben@simtec.co.uk> */
.atag_offset = 0x100,
+ .nr_irqs = NR_IRQS_S3C2410,
.map_io = bast_map_io,
.init_irq = s3c2410_init_irq,
.init_machine = bast_init,
#include <linux/platform_data/spi-s3c64xx.h>
#include "cpu.h"
-#include <mach/irqs.h>
+#include "irqs.h"
#include "crag6410.h"
#include "map.h"
#include "regs-gpio.h"
#include "gpio-samsung.h"
-#include <mach/irqs.h>
+#include "irqs.h"
#include "fb.h"
#include "sdhci.h"
MACHINE_START(NEO1973_GTA02, "GTA02")
/* Maintainer: Nelson Castillo <arhuaco@freaks-unidos.net> */
.atag_offset = 0x100,
+ .nr_irqs = NR_IRQS_S3C2442,
.map_io = gta02_map_io,
.init_irq = s3c2442_init_irq,
.init_machine = gta02_machine_init,
MACHINE_START(H1940, "IPAQ-H1940")
/* Maintainer: Ben Dooks <ben-linux@fluff.org> */
.atag_offset = 0x100,
+ .nr_irqs = NR_IRQS_S3C2410,
.map_io = h1940_map_io,
.reserve = h1940_reserve,
.init_irq = s3c2410_init_irq,
#include <video/samsung_fimd.h>
#include "map.h"
-#include <mach/irqs.h>
+#include "irqs.h"
#include <asm/irq.h>
#include <asm/mach-types.h>
MACHINE_START(JIVE, "JIVE")
/* Maintainer: Ben Dooks <ben-linux@fluff.org> */
.atag_offset = 0x100,
-
+ .nr_irqs = NR_IRQS_S3C2412,
.init_irq = s3c2412_init_irq,
.map_io = jive_map_io,
.init_machine = jive_machine_init,
#include "regs-gpio.h"
#include <linux/platform_data/leds-s3c24xx.h>
-#include <mach/irqs.h>
+#include "irqs.h"
#include "gpio-samsung.h"
#include <linux/platform_data/mtd-nand-s3c2410.h>
#include <linux/platform_data/i2c-s3c2410.h>
MACHINE_START(MINI2440, "MINI2440")
/* Maintainer: Michel Pollet <buserror@gmail.com> */
.atag_offset = 0x100,
+ .nr_irqs = NR_IRQS_S3C2440,
.map_io = mini2440_map_io,
.init_machine = mini2440_init,
.init_irq = s3c2440_init_irq,
#include <linux/platform_data/mmc-sdhci-s3c.h>
#include "sdhci.h"
#include <linux/platform_data/touchscreen-s3c2410.h>
-#include <mach/irqs.h>
+#include "irqs.h"
#include <video/platform_lcd.h>
#include <video/samsung_fimd.h>
Ben Dooks <ben-linux@fluff.org>
*/
.atag_offset = 0x100,
+ .nr_irqs = NR_IRQS_S3C2410,
.init_time = n30_init_time,
.init_machine = n30_init,
.init_irq = s3c2410_init_irq,
/* Maintainer: Christer Weinigel <christer@weinigel.se>
*/
.atag_offset = 0x100,
+ .nr_irqs = NR_IRQS_S3C2410,
.init_time = n30_init_time,
.init_machine = n30_init,
.init_irq = s3c2410_init_irq,
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
-#include <mach/irqs.h>
+#include "irqs.h"
#include "map.h"
#include <asm/irq.h>
MACHINE_START(NEXCODER_2440, "NexVision - Nexcoder 2440")
/* Maintainer: Guillaume GOURAT <guillaume.gourat@nexvision.tv> */
.atag_offset = 0x100,
+ .nr_irqs = NR_IRQS_S3C2440,
.map_io = nexcoder_map_io,
.init_machine = nexcoder_init,
.init_irq = s3c2440_init_irq,
MACHINE_START(OSIRIS, "Simtec-OSIRIS")
/* Maintainer: Ben Dooks <ben@simtec.co.uk> */
.atag_offset = 0x100,
+ .nr_irqs = NR_IRQS_S3C2440,
.map_io = osiris_map_io,
.init_irq = s3c2440_init_irq,
.init_machine = osiris_init,
MACHINE_START(OTOM, "Nex Vision - Otom 1.1")
/* Maintainer: Guillaume GOURAT <guillaume.gourat@nexvision.tv> */
.atag_offset = 0x100,
+ .nr_irqs = NR_IRQS_S3C2410,
.map_io = otom11_map_io,
.init_machine = otom11_init,
.init_irq = s3c2410_init_irq,
MACHINE_START(QT2410, "QT2410")
.atag_offset = 0x100,
+ .nr_irqs = NR_IRQS_S3C2410,
.map_io = qt2410_map_io,
.init_irq = s3c2410_init_irq,
.init_machine = qt2410_machine_init,
#include "map.h"
#include "regs-gpio.h"
#include "gpio-samsung.h"
-#include <mach/irqs.h>
+#include "irqs.h"
#include <linux/soc/samsung/s3c-adc.h>
#include "cpu.h"
MACHINE_START(RX1950, "HP iPAQ RX1950")
/* Maintainers: Vasily Khoruzhick */
.atag_offset = 0x100,
+ .nr_irqs = NR_IRQS_S3C2442,
.map_io = rx1950_map_io,
.reserve = rx1950_reserve,
.init_irq = s3c2442_init_irq,
MACHINE_START(RX3715, "IPAQ-RX3715")
/* Maintainer: Ben Dooks <ben-linux@fluff.org> */
.atag_offset = 0x100,
+ .nr_irqs = NR_IRQS_S3C2440,
.map_io = rx3715_map_io,
.reserve = rx3715_reserve,
.init_irq = s3c2440_init_irq,
#include <asm/mach/arch.h>
#include <video/samsung_fimd.h>
-#include <mach/irqs.h>
+#include "irqs.h"
#include "map.h"
#include "regs-gpio.h"
#include "gpio-samsung.h"
#include <asm/mach/arch.h>
#include <video/samsung_fimd.h>
-#include <mach/irqs.h>
+#include "irqs.h"
#include "map.h"
#include "regs-gpio.h"
#include "gpio-samsung.h"
* to SMDK2410 */
/* Maintainer: Jonas Dietsche */
.atag_offset = 0x100,
+ .nr_irqs = NR_IRQS_S3C2410,
.map_io = smdk2410_map_io,
.init_irq = s3c2410_init_irq,
.init_machine = smdk2410_init,
MACHINE_START(S3C2413, "S3C2413")
/* Maintainer: Ben Dooks <ben-linux@fluff.org> */
.atag_offset = 0x100,
+ .nr_irqs = NR_IRQS_S3C2412,
.fixup = smdk2413_fixup,
.init_irq = s3c2412_init_irq,
MACHINE_START(SMDK2412, "SMDK2412")
/* Maintainer: Ben Dooks <ben-linux@fluff.org> */
.atag_offset = 0x100,
+ .nr_irqs = NR_IRQS_S3C2412,
.fixup = smdk2413_fixup,
.init_irq = s3c2412_init_irq,
MACHINE_START(SMDK2413, "SMDK2413")
/* Maintainer: Ben Dooks <ben-linux@fluff.org> */
.atag_offset = 0x100,
+ .nr_irqs = NR_IRQS_S3C2412,
.fixup = smdk2413_fixup,
.init_irq = s3c2412_init_irq,
MACHINE_START(SMDK2416, "SMDK2416")
/* Maintainer: Yauhen Kharuzhy <jekhor@gmail.com> */
.atag_offset = 0x100,
+ .nr_irqs = NR_IRQS_S3C2416,
.init_irq = s3c2416_init_irq,
.map_io = smdk2416_map_io,
MACHINE_START(S3C2440, "SMDK2440")
/* Maintainer: Ben Dooks <ben-linux@fluff.org> */
.atag_offset = 0x100,
+ .nr_irqs = NR_IRQS_S3C2440,
.init_irq = s3c2440_init_irq,
.map_io = smdk2440_map_io,
MACHINE_START(SMDK2443, "SMDK2443")
/* Maintainer: Ben Dooks <ben-linux@fluff.org> */
.atag_offset = 0x100,
-
+ .nr_irqs = NR_IRQS_S3C2443,
.init_irq = s3c2443_init_irq,
.map_io = smdk2443_map_io,
.init_machine = smdk2443_machine_init,
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
-#include <mach/irqs.h>
+#include "irqs.h"
#include "map.h"
#include "devs.h"
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
-#include <mach/irqs.h>
+#include "irqs.h"
#include "map.h"
#include <asm/irq.h>
MACHINE_START(TCT_HAMMER, "TCT_HAMMER")
.atag_offset = 0x100,
+ .nr_irqs = NR_IRQS_S3C2410,
.map_io = tct_hammer_map_io,
.init_irq = s3c2410_init_irq,
.init_machine = tct_hammer_init,
MACHINE_START(VR1000, "Thorcom-VR1000")
/* Maintainer: Ben Dooks <ben@simtec.co.uk> */
.atag_offset = 0x100,
+ .nr_irqs = NR_IRQS_S3C2410,
.map_io = vr1000_map_io,
.init_machine = vr1000_init,
.init_irq = s3c2410_init_irq,
MACHINE_START(VSTMS, "VSTMS")
.atag_offset = 0x100,
+ .nr_irqs = NR_IRQS_S3C2412,
.fixup = vstms_fixup,
.init_irq = s3c2412_init_irq,
#include <linux/of.h>
#include "cpu.h"
-#include <mach/irqs.h>
+#include "irqs.h"
#include "map.h"
#include "regs-sys-s3c64xx.h"
#include "regs-clock.h"
#include "regs-irq-s3c24xx.h"
-#include <mach/irqs.h>
+#include "irqs.h"
static inline void s3c_pm_debug_init_uart(void)
{
#include <asm/cacheflush.h>
#include <asm/irq.h>
-#include <mach/irqs.h>
+#include "irqs.h"
#include "regs-gpio.h"
#include "cpu.h"
#include <linux/pm_domain.h>
#include "map.h"
-#include <mach/irqs.h>
+#include "irqs.h"
#include "cpu.h"
#include "devs.h"
#include "map.h"
#include "regs-clock.h"
#include "regs-irq.h"
-#include <mach/irqs.h>
+#include "irqs.h"
#include <asm/irq.h>
#include "map.h"
#include "gpio-samsung.h"
-#include <mach/irqs.h>
+#include "irqs.h"
#include <asm/irq.h>
#include <asm/system_misc.h>
#define __ARCH_ARM_MACH_S3C24XX_COMMON_H __FILE__
#include <linux/reboot.h>
-#include <mach/irqs.h>
+#include "irqs.h"
struct s3c2410_uartcfg;
#include <asm/system_misc.h>
#include "map.h"
-#include <mach/irqs.h>
+#include "irqs.h"
#include "regs-gpio.h"
#include "gpio-samsung.h"
#include <asm/mach/irq.h>
#include "gpio-samsung.h"
-#include <mach/irqs.h>
+#include "irqs.h"
#include <asm/irq.h>
#include <linux/platform_data/usb-ohci-s3c2410.h>
projects / linux.git / commitdiff