arm64: dts: hi3798cv200: add cache info

During boot, the kernel complains:

[    0.044029] cacheinfo: Unable to detect cache hierarchy for CPU 0

So add L1/L2 cache info to the dts according to the datasheet. (32KiB L1
i-cache + 32 KiB L1 d-cache + 512 KiB L2 unified cache)

With this patch, the line above is gone and the following info is added
to the output of `lscpu`:

Caches (sum of all):
  L1d:                   128 KiB (4 instances)
  L1i:                   128 KiB (4 instances)
  L2:                    512 KiB (1 instance)

Signed-off-by: Yang Xiwen <forbidden405@outlook.com>
Link: https://lore.kernel.org/r/20240219-cache-v3-3-a33c57534ae9@outlook.com
[krzysztof: drop Fixes/cc-stable, because this is a missing feature, not
 a fix]
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
index fc64d2fa99eb11d510ed323d8bab057edbb9c0a8..f6bc001c3832632bf2262286daedd84238ba59af 100644 (file)
--- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
@@ -31,6 +31,13 @@
                        device_type = "cpu";
                        reg = <0x0 0x0>;
                        enable-method = "psci";
+                       d-cache-size = <0x8000>; /* 32 KiB */
+                       d-cache-line-size = <64>;
+                       d-cache-sets = <128>;
+                       i-cache-size = <0x8000>; /* 32 KiB */
+                       i-cache-line-size = <64>;
+                       i-cache-sets = <256>;
+                       next-level-cache = <&L2>;
                };
 
                cpu@1 {
@@ -38,6 +45,13 @@
                        device_type = "cpu";
                        reg = <0x0 0x1>;
                        enable-method = "psci";
+                       d-cache-size = <0x8000>; /* 32 KiB */
+                       d-cache-line-size = <64>;
+                       d-cache-sets = <128>;
+                       i-cache-size = <0x8000>; /* 32 KiB */
+                       i-cache-line-size = <64>;
+                       i-cache-sets = <256>;
+                       next-level-cache = <&L2>;
                };
 
                cpu@2 {
@@ -45,6 +59,13 @@
                        device_type = "cpu";
                        reg = <0x0 0x2>;
                        enable-method = "psci";
+                       d-cache-size = <0x8000>; /* 32 KiB */
+                       d-cache-line-size = <64>;
+                       d-cache-sets = <128>;
+                       i-cache-size = <0x8000>; /* 32 KiB */
+                       i-cache-line-size = <64>;
+                       i-cache-sets = <256>;
+                       next-level-cache = <&L2>;
                };
 
                cpu@3 {
@@ -52,9 +73,25 @@
                        device_type = "cpu";
                        reg = <0x0 0x3>;
                        enable-method = "psci";
+                       d-cache-size = <0x8000>; /* 32 KiB */
+                       d-cache-line-size = <64>;
+                       d-cache-sets = <128>;
+                       i-cache-size = <0x8000>; /* 32 KiB */
+                       i-cache-line-size = <64>;
+                       i-cache-sets = <256>;
+                       next-level-cache = <&L2>;
                };
        };
 
+       L2: l2-cache {
+               compatible = "cache";
+               cache-unified;
+               cache-size = <0x80000>; /* 512 KiB */
+               cache-line-size = <64>;
+               cache-sets = <512>;
+               cache-level = <2>;
+       };
+
        gic: interrupt-controller@f1001000 {
                compatible = "arm,gic-400";
                reg = <0x0 0xf1001000 0x0 0x1000>,  /* GICD */