drm/amdgpu: Remove else after return statement in 'gfx_v10_0_check_grbm_cam_remapping'

Fix below checkpatch warnings:

WARNING: else is not generally useful after a break or return
+                       return true;
+               } else {

WARNING: else is not generally useful after a break or return
+                       return true;
+               } else {

Cc: Christian König <christian.koenig@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 44af8022b89fa96900f751c3e224b5b82995f2f4..3909fb769b952eb44fbb9f7c589eda0fd1b89868 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -6936,10 +6936,8 @@ static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
                if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) {
                        WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD , data);
                        return true;
-               } else {
-                       WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data);
-                       return false;
                }
+               WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data);
                break;
        case IP_VERSION(10, 3, 1):
        case IP_VERSION(10, 3, 3):
@@ -6954,12 +6952,12 @@ static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
                if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) {
                        WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
                        return true;
-               } else {
-                       WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data);
-                       return false;
                }
+               WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data);
                break;
        }
+
+       return false;
 }
 
 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)