media: verisilicon: Fix some typos
authorrenjun wang <renjunw0@foxmail.com>
Sat, 16 Dec 2023 04:18:05 +0000 (12:18 +0800)
committerHans Verkuil <hverkuil-cisco@xs4all.nl>
Mon, 5 Feb 2024 11:57:44 +0000 (12:57 +0100)
Function hantro_g1_h264_dec_prepare_table() does not exist,
should be replaced with hantro_h264_dec_init().

The register name av1_ulticore_tile_col confused sometimes,
although not be used corrently. The correct name should be
av1_multicore_tile_col.

Signed-off-by: renjun wang <renjunw0@foxmail.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
drivers/media/platform/verisilicon/hantro_g1_h264_dec.c
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
drivers/media/platform/verisilicon/rockchip_vpu981_regs.h

index 9de7f05eff2a6fe115a8a4d3d3669016d6df5319..ad5c1a6634f5c816740d3220ade01632a5cd6c0b 100644 (file)
@@ -243,7 +243,7 @@ static void set_buffers(struct hantro_ctx *ctx, struct vb2_v4l2_buffer *src_buf)
                vdpu_write_relaxed(vpu, dst_dma + offset, G1_REG_ADDR_DIR_MV);
        }
 
-       /* Auxiliary buffer prepared in hantro_g1_h264_dec_prepare_table(). */
+       /* Auxiliary buffer prepared in hantro_h264_dec_init(). */
        vdpu_write_relaxed(vpu, ctx->h264_dec.priv.dma, G1_REG_ADDR_QTABLE);
 }
 
index 46c1a83bcc4e009d065b13de04634a7df1d7ccdc..6da87f5184bcbc777788fe5321bca46da36c647f 100644 (file)
@@ -460,7 +460,7 @@ static void set_buffers(struct hantro_ctx *ctx, struct vb2_v4l2_buffer *src_buf)
                vdpu_write_relaxed(vpu, dst_dma + offset, VDPU_REG_DIR_MV_BASE);
        }
 
-       /* Auxiliary buffer prepared in hantro_g1_h264_dec_prepare_table(). */
+       /* Auxiliary buffer prepared in hantro_h264_dec_init(). */
        vdpu_write_relaxed(vpu, ctx->h264_dec.priv.dma, VDPU_REG_QTABLE_BASE);
 }
 
index 182e6c830ff696d06b97431371750b4eedb413ff..850ff0f844248d7b74b5dc1aa84356531ff25d58 100644 (file)
 #define av1_mcomp_filt_type            AV1_DEC_REG(11, 8, 0x7)
 #define av1_multicore_expect_context_update    AV1_DEC_REG(11, 11, 0x1)
 #define av1_multicore_sbx_offset       AV1_DEC_REG(11, 12, 0x7f)
-#define av1_ulticore_tile_col          AV1_DEC_REG(11, 19, 0x7f)
+#define av1_multicore_tile_col         AV1_DEC_REG(11, 19, 0x7f)
 #define av1_transform_mode             AV1_DEC_REG(11, 27, 0x7)
 #define av1_dec_tile_size_mag          AV1_DEC_REG(11, 30, 0x3)