target/arm: Set SIMDMISC and FPMISC for 32-bit -cpu max
authorRichard Henderson <richard.henderson@linaro.org>
Tue, 26 Mar 2019 12:53:26 +0000 (12:53 +0000)
committerPeter Maydell <peter.maydell@linaro.org>
Tue, 26 Mar 2019 12:53:26 +0000 (12:53 +0000)
Fixes: https://bugs.launchpad.net/bugs/1821430
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20190325161338.6536-1-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target/arm/cpu.c

index 504a4771fbd34fb92afed97baeb18a6d4bf1a47a..415578219746e8ffa57e8eeb22e63afdb0a242ec 100644 (file)
@@ -2028,6 +2028,11 @@ static void arm_max_initfn(Object *obj)
             t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
             cpu->isar.id_isar6 = t;
 
+            t = cpu->isar.mvfr2;
+            t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
+            t = FIELD_DP32(t, MVFR2, FPMISC, 4);   /* FP MaxNum */
+            cpu->isar.mvfr2 = t;
+
             t = cpu->id_mmfr4;
             t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
             cpu->id_mmfr4 = t;