arm64: dts: imx8mm: Add display pipeline components

Add LCDIF scanout engine and DSIM bridge nodes for i.MX8M Mini.
This makes the DSI display pipeline available on this SoC.

Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index a9552867e547cdc07fec4eba161b45fbfa8af4a7..ba06b5273b9127c0d3bfcb4b027a1e91efd749df 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -1119,6 +1119,61 @@
                        #size-cells = <1>;
                        ranges = <0x32c00000 0x32c00000 0x400000>;
 
+                       lcdif: lcdif@32e00000 {
+                               compatible = "fsl,imx8mm-lcdif", "fsl,imx6sx-lcdif";
+                               reg = <0x32e00000 0x10000>;
+                               clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL>,
+                                        <&clk IMX8MM_CLK_DISP_APB_ROOT>,
+                                        <&clk IMX8MM_CLK_DISP_AXI_ROOT>;
+                               clock-names = "pix", "axi", "disp_axi";
+                               assigned-clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL>,
+                                                 <&clk IMX8MM_CLK_DISP_AXI>,
+                                                 <&clk IMX8MM_CLK_DISP_APB>;
+                               assigned-clock-parents = <&clk IMX8MM_VIDEO_PLL1_OUT>,
+                                                        <&clk IMX8MM_SYS_PLL2_1000M>,
+                                                        <&clk IMX8MM_SYS_PLL1_800M>;
+                               assigned-clock-rates = <594000000>, <500000000>, <200000000>;
+                               interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+                               power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_LCDIF>;
+                               status = "disabled";
+
+                               port {
+                                       lcdif_to_dsim: endpoint {
+                                               remote-endpoint = <&dsim_from_lcdif>;
+                                       };
+                               };
+                       };
+
+                       mipi_dsi: dsi@32e10000 {
+                               compatible = "fsl,imx8mm-mipi-dsim";
+                               reg = <0x32e10000 0x400>;
+                               clocks = <&clk IMX8MM_CLK_DSI_CORE>,
+                                        <&clk IMX8MM_CLK_DSI_PHY_REF>;
+                               clock-names = "bus_clk", "sclk_mipi";
+                               assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>,
+                                                 <&clk IMX8MM_CLK_DSI_PHY_REF>;
+                               assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
+                                                        <&clk IMX8MM_CLK_24M>;
+                               assigned-clock-rates = <266000000>, <24000000>;
+                               samsung,pll-clock-frequency = <24000000>;
+                               interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+                               power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_DSI>;
+                               status = "disabled";
+
+                               ports {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+
+                                       port@0 {
+                                               reg = <0>;
+
+                                               dsim_from_lcdif: endpoint {
+                                                       remote-endpoint = <&lcdif_to_dsim>;
+                                               };
+                                       };
+                               };
+                       };
+
                        csi: csi@32e20000 {
                                compatible = "fsl,imx8mm-csi", "fsl,imx7-csi";
                                reg = <0x32e20000 0x1000>;