/* QPHY_START_CONTROL bits */
 #define SERDES_START                           BIT(0)
 #define PCS_START                              BIT(1)
-/* QPHY_PCS_STATUS bit */
-#define PHYSTATUS                              BIT(6)
 /* QPHY_PCS_READY_STATUS bit */
 #define PCS_READY                              BIT(0)
 
 
        unsigned int start_ctrl;
        unsigned int pwrdn_ctrl;
-       /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */
-       unsigned int phy_status;
 
        /* true, if PCS block has no separate SW_RESET register */
        bool no_pcs_sw_reset;
 
        .start_ctrl             = SERDES_START,
        .pwrdn_ctrl             = SW_PWRDN,
-       .phy_status             = PHYSTATUS,
 
        .no_pcs_sw_reset        = true,
 };
 
        .start_ctrl             = SERDES_START,
        .pwrdn_ctrl             = SW_PWRDN,
-       .phy_status             = PHYSTATUS,
 
        .no_pcs_sw_reset        = true,
 };
 
        .start_ctrl             = SERDES_START,
        .pwrdn_ctrl             = SW_PWRDN,
-       .phy_status             = PHYSTATUS,
 };
 
 static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
 
        .start_ctrl             = SERDES_START,
        .pwrdn_ctrl             = SW_PWRDN,
-       .phy_status             = PHYSTATUS,
 };
 
 static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
 
        .start_ctrl             = SERDES_START,
        .pwrdn_ctrl             = SW_PWRDN,
-       .phy_status             = PHYSTATUS,
 };
 
 static void qmp_ufs_configure_lane(void __iomem *base,