accel/ivpu/37xx: White space cleanup

No functional change, adjust code formatting so that defines line up
nicely to improve code readability.

Reviewed-by: Karol Wachowski <karol.wachowski@linux.intel.com>
Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com>
Signed-off-by: Stanislaw Gruszka <stanislaw.gruszka@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230901094957.168898-11-stanislaw.gruszka@linux.intel.com

diff --git a/drivers/accel/ivpu/ivpu_hw_37xx_reg.h b/drivers/accel/ivpu/ivpu_hw_37xx_reg.h
index 0f106f192f7ca545a63e9c0b654e8a1a7835ccce..531a68c1cce8f938c81c3d66d19d4a1916d4efad 100644 (file)
--- a/drivers/accel/ivpu/ivpu_hw_37xx_reg.h
+++ b/drivers/accel/ivpu/ivpu_hw_37xx_reg.h
@@ -8,65 +8,65 @@
 
 #include <linux/bits.h>
 
-#define VPU_37XX_BUTTRESS_INTERRUPT_TYPE                                       0x00000000u
+#define VPU_37XX_BUTTRESS_INTERRUPT_TYPE                               0x00000000u
 
-#define VPU_37XX_BUTTRESS_INTERRUPT_STAT                                       0x00000004u
-#define VPU_37XX_BUTTRESS_INTERRUPT_STAT_FREQ_CHANGE_MASK                      BIT_MASK(0)
+#define VPU_37XX_BUTTRESS_INTERRUPT_STAT                               0x00000004u
+#define VPU_37XX_BUTTRESS_INTERRUPT_STAT_FREQ_CHANGE_MASK              BIT_MASK(0)
 #define VPU_37XX_BUTTRESS_INTERRUPT_STAT_ATS_ERR_MASK                  BIT_MASK(1)
 #define VPU_37XX_BUTTRESS_INTERRUPT_STAT_UFI_ERR_MASK                  BIT_MASK(2)
 
-#define VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD0                                      0x00000008u
-#define VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD0_MIN_RATIO_MASK                       GENMASK(15, 0)
-#define VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD0_MAX_RATIO_MASK                       GENMASK(31, 16)
+#define VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD0                              0x00000008u
+#define VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD0_MIN_RATIO_MASK               GENMASK(15, 0)
+#define VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD0_MAX_RATIO_MASK               GENMASK(31, 16)
 
-#define VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD1                                      0x0000000cu
-#define VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD1_TARGET_RATIO_MASK                    GENMASK(15, 0)
-#define VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD1_EPP_MASK                             GENMASK(31, 16)
+#define VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD1                              0x0000000cu
+#define VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD1_TARGET_RATIO_MASK            GENMASK(15, 0)
+#define VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD1_EPP_MASK                     GENMASK(31, 16)
 
-#define VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD2                                      0x00000010u
+#define VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD2                              0x00000010u
 #define VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD2_CONFIG_MASK                  GENMASK(15, 0)
 
-#define VPU_37XX_BUTTRESS_WP_REQ_CMD                                           0x00000014u
+#define VPU_37XX_BUTTRESS_WP_REQ_CMD                                   0x00000014u
 #define VPU_37XX_BUTTRESS_WP_REQ_CMD_SEND_MASK                         BIT_MASK(0)
 
 #define VPU_37XX_BUTTRESS_WP_DOWNLOAD                                  0x00000018u
 #define VPU_37XX_BUTTRESS_WP_DOWNLOAD_TARGET_RATIO_MASK                        GENMASK(15, 0)
 
 #define VPU_37XX_BUTTRESS_CURRENT_PLL                                  0x0000001cu
-#define VPU_37XX_BUTTRESS_CURRENT_PLL_RATIO_MASK                               GENMASK(15, 0)
+#define VPU_37XX_BUTTRESS_CURRENT_PLL_RATIO_MASK                       GENMASK(15, 0)
 
-#define VPU_37XX_BUTTRESS_PLL_ENABLE                                           0x00000020u
+#define VPU_37XX_BUTTRESS_PLL_ENABLE                                   0x00000020u
 
-#define VPU_37XX_BUTTRESS_FMIN_FUSE                                            0x00000024u
-#define VPU_37XX_BUTTRESS_FMIN_FUSE_MIN_RATIO_MASK                             GENMASK(7, 0)
-#define VPU_37XX_BUTTRESS_FMIN_FUSE_PN_RATIO_MASK                              GENMASK(15, 8)
+#define VPU_37XX_BUTTRESS_FMIN_FUSE                                    0x00000024u
+#define VPU_37XX_BUTTRESS_FMIN_FUSE_MIN_RATIO_MASK                     GENMASK(7, 0)
+#define VPU_37XX_BUTTRESS_FMIN_FUSE_PN_RATIO_MASK                      GENMASK(15, 8)
 
-#define VPU_37XX_BUTTRESS_FMAX_FUSE                                            0x00000028u
-#define VPU_37XX_BUTTRESS_FMAX_FUSE_MAX_RATIO_MASK                             GENMASK(7, 0)
+#define VPU_37XX_BUTTRESS_FMAX_FUSE                                    0x00000028u
+#define VPU_37XX_BUTTRESS_FMAX_FUSE_MAX_RATIO_MASK                     GENMASK(7, 0)
 
-#define VPU_37XX_BUTTRESS_TILE_FUSE                                            0x0000002cu
+#define VPU_37XX_BUTTRESS_TILE_FUSE                                    0x0000002cu
 #define VPU_37XX_BUTTRESS_TILE_FUSE_VALID_MASK                         BIT_MASK(0)
-#define VPU_37XX_BUTTRESS_TILE_FUSE_SKU_MASK                                   GENMASK(3, 2)
+#define VPU_37XX_BUTTRESS_TILE_FUSE_SKU_MASK                           GENMASK(3, 2)
 
-#define VPU_37XX_BUTTRESS_LOCAL_INT_MASK                                       0x00000030u
-#define VPU_37XX_BUTTRESS_GLOBAL_INT_MASK                                      0x00000034u
+#define VPU_37XX_BUTTRESS_LOCAL_INT_MASK                               0x00000030u
+#define VPU_37XX_BUTTRESS_GLOBAL_INT_MASK                              0x00000034u
 
-#define VPU_37XX_BUTTRESS_PLL_STATUS                                           0x00000040u
+#define VPU_37XX_BUTTRESS_PLL_STATUS                                   0x00000040u
 #define VPU_37XX_BUTTRESS_PLL_STATUS_LOCK_MASK                         BIT_MASK(1)
 
-#define VPU_37XX_BUTTRESS_VPU_STATUS                                           0x00000044u
+#define VPU_37XX_BUTTRESS_VPU_STATUS                                   0x00000044u
 #define VPU_37XX_BUTTRESS_VPU_STATUS_READY_MASK                                BIT_MASK(0)
 #define VPU_37XX_BUTTRESS_VPU_STATUS_IDLE_MASK                         BIT_MASK(1)
 
-#define VPU_37XX_BUTTRESS_VPU_D0I3_CONTROL                                     0x00000060u
-#define VPU_37XX_BUTTRESS_VPU_D0I3_CONTROL_INPROGRESS_MASK                     BIT_MASK(0)
-#define VPU_37XX_BUTTRESS_VPU_D0I3_CONTROL_I3_MASK                             BIT_MASK(2)
+#define VPU_37XX_BUTTRESS_VPU_D0I3_CONTROL                             0x00000060u
+#define VPU_37XX_BUTTRESS_VPU_D0I3_CONTROL_INPROGRESS_MASK             BIT_MASK(0)
+#define VPU_37XX_BUTTRESS_VPU_D0I3_CONTROL_I3_MASK                     BIT_MASK(2)
 
 #define VPU_37XX_BUTTRESS_VPU_IP_RESET                                 0x00000050u
-#define VPU_37XX_BUTTRESS_VPU_IP_RESET_TRIGGER_MASK                            BIT_MASK(0)
+#define VPU_37XX_BUTTRESS_VPU_IP_RESET_TRIGGER_MASK                    BIT_MASK(0)
 
 #define VPU_37XX_BUTTRESS_VPU_TELEMETRY_OFFSET                         0x00000080u
-#define VPU_37XX_BUTTRESS_VPU_TELEMETRY_SIZE                                   0x00000084u
+#define VPU_37XX_BUTTRESS_VPU_TELEMETRY_SIZE                           0x00000084u
 #define VPU_37XX_BUTTRESS_VPU_TELEMETRY_ENABLE                         0x00000088u
 
 #define VPU_37XX_BUTTRESS_ATS_ERR_LOG_0                                        0x000000a0u
@@ -74,9 +74,9 @@
 #define VPU_37XX_BUTTRESS_ATS_ERR_CLEAR                                        0x000000a8u
 
 #define VPU_37XX_BUTTRESS_UFI_ERR_LOG                                  0x000000b0u
-#define VPU_37XX_BUTTRESS_UFI_ERR_LOG_CQ_ID_MASK                               GENMASK(11, 0)
-#define VPU_37XX_BUTTRESS_UFI_ERR_LOG_AXI_ID_MASK                              GENMASK(19, 12)
-#define VPU_37XX_BUTTRESS_UFI_ERR_LOG_OPCODE_MASK                              GENMASK(24, 20)
+#define VPU_37XX_BUTTRESS_UFI_ERR_LOG_CQ_ID_MASK                       GENMASK(11, 0)
+#define VPU_37XX_BUTTRESS_UFI_ERR_LOG_AXI_ID_MASK                      GENMASK(19, 12)
+#define VPU_37XX_BUTTRESS_UFI_ERR_LOG_OPCODE_MASK                      GENMASK(24, 20)
 
 #define VPU_37XX_BUTTRESS_UFI_ERR_CLEAR                                        0x000000b4u
 
@@ -140,9 +140,9 @@
 #define VPU_37XX_HOST_SS_ICB_STATUS_0_TIMER_2_INT_MASK                 BIT_MASK(2)
 #define VPU_37XX_HOST_SS_ICB_STATUS_0_TIMER_3_INT_MASK                 BIT_MASK(3)
 #define VPU_37XX_HOST_SS_ICB_STATUS_0_HOST_IPC_FIFO_INT_MASK           BIT_MASK(4)
-#define VPU_37XX_HOST_SS_ICB_STATUS_0_MMU_IRQ_0_INT_MASK                       BIT_MASK(5)
-#define VPU_37XX_HOST_SS_ICB_STATUS_0_MMU_IRQ_1_INT_MASK                       BIT_MASK(6)
-#define VPU_37XX_HOST_SS_ICB_STATUS_0_MMU_IRQ_2_INT_MASK                       BIT_MASK(7)
+#define VPU_37XX_HOST_SS_ICB_STATUS_0_MMU_IRQ_0_INT_MASK               BIT_MASK(5)
+#define VPU_37XX_HOST_SS_ICB_STATUS_0_MMU_IRQ_1_INT_MASK               BIT_MASK(6)
+#define VPU_37XX_HOST_SS_ICB_STATUS_0_MMU_IRQ_2_INT_MASK               BIT_MASK(7)
 #define VPU_37XX_HOST_SS_ICB_STATUS_0_NOC_FIREWALL_INT_MASK            BIT_MASK(8)
 #define VPU_37XX_HOST_SS_ICB_STATUS_0_CPU_INT_REDIRECT_0_INT_MASK      BIT_MASK(30)
 #define VPU_37XX_HOST_SS_ICB_STATUS_0_CPU_INT_REDIRECT_1_INT_MASK      BIT_MASK(31)
@@ -164,14 +164,14 @@
 #define VPU_37XX_HOST_SS_TIM_IPC_FIFO_STAT_FILL_LEVEL_MASK             GENMASK(23, 16)
 #define VPU_37XX_HOST_SS_TIM_IPC_FIFO_STAT_RSVD0_MASK                  GENMASK(31, 24)
 
-#define VPU_37XX_HOST_SS_AON_PWR_ISO_EN0                                       0x00030020u
+#define VPU_37XX_HOST_SS_AON_PWR_ISO_EN0                               0x00030020u
 #define VPU_37XX_HOST_SS_AON_PWR_ISO_EN0_MSS_CPU_MASK                  BIT_MASK(3)
 
 #define VPU_37XX_HOST_SS_AON_PWR_ISLAND_EN0                            0x00030024u
-#define VPU_37XX_HOST_SS_AON_PWR_ISLAND_EN0_MSS_CPU_MASK                       BIT_MASK(3)
+#define VPU_37XX_HOST_SS_AON_PWR_ISLAND_EN0_MSS_CPU_MASK               BIT_MASK(3)
 
 #define VPU_37XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0                    0x00030028u
-#define VPU_37XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0_MSS_CPU_MASK               BIT_MASK(3)
+#define VPU_37XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0_MSS_CPU_MASK       BIT_MASK(3)
 
 #define VPU_37XX_HOST_SS_AON_PWR_ISLAND_STATUS0                                0x0003002cu
 #define VPU_37XX_HOST_SS_AON_PWR_ISLAND_STATUS0_MSS_CPU_MASK           BIT_MASK(3)
@@ -187,7 +187,7 @@
 #define VPU_37XX_HOST_SS_LOADING_ADDRESS_LO_IOSF_RS_ID_MASK            GENMASK(2, 1)
 #define VPU_37XX_HOST_SS_LOADING_ADDRESS_LO_IMAGE_LOCATION_MASK                GENMASK(31, 3)
 
-#define VPU_37XX_HOST_SS_WORKPOINT_CONFIG_MIRROR                               0x00082020u
+#define VPU_37XX_HOST_SS_WORKPOINT_CONFIG_MIRROR                       0x00082020u
 #define VPU_37XX_HOST_SS_WORKPOINT_CONFIG_MIRROR_FINAL_PLL_FREQ_MASK   GENMASK(15, 0)
 #define VPU_37XX_HOST_SS_WORKPOINT_CONFIG_MIRROR_CONFIG_ID_MASK                GENMASK(31, 16)
 
@@ -196,13 +196,13 @@
 #define VPU_37XX_HOST_MMU_IDR3                                         0x0020000cu
 #define VPU_37XX_HOST_MMU_IDR5                                         0x00200014u
 #define VPU_37XX_HOST_MMU_CR0                                          0x00200020u
-#define VPU_37XX_HOST_MMU_CR0ACK                                               0x00200024u
+#define VPU_37XX_HOST_MMU_CR0ACK                                       0x00200024u
 #define VPU_37XX_HOST_MMU_CR1                                          0x00200028u
 #define VPU_37XX_HOST_MMU_CR2                                          0x0020002cu
 #define VPU_37XX_HOST_MMU_IRQ_CTRL                                     0x00200050u
 #define VPU_37XX_HOST_MMU_IRQ_CTRLACK                                  0x00200054u
 
-#define VPU_37XX_HOST_MMU_GERROR                                               0x00200060u
+#define VPU_37XX_HOST_MMU_GERROR                                       0x00200060u
 #define VPU_37XX_HOST_MMU_GERROR_CMDQ_MASK                             BIT_MASK(0)
 #define VPU_37XX_HOST_MMU_GERROR_EVTQ_ABT_MASK                         BIT_MASK(2)
 #define VPU_37XX_HOST_MMU_GERROR_PRIQ_ABT_MASK                         BIT_MASK(3)
@@ -226,8 +226,8 @@
 
 #define VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES                             0x00360000u
 #define VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES_CACHE_OVERRIDE_EN_MASK      BIT_MASK(0)
-#define VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES_AWCACHE_OVERRIDE_MASK               BIT_MASK(1)
-#define VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES_ARCACHE_OVERRIDE_MASK               BIT_MASK(2)
+#define VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES_AWCACHE_OVERRIDE_MASK       BIT_MASK(1)
+#define VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES_ARCACHE_OVERRIDE_MASK       BIT_MASK(2)
 #define VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES_NOSNOOP_OVERRIDE_EN_MASK    BIT_MASK(3)
 #define VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES_AW_NOSNOOP_OVERRIDE_MASK    BIT_MASK(4)
 #define VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES_AR_NOSNOOP_OVERRIDE_MASK    BIT_MASK(5)
@@ -246,11 +246,11 @@
 #define VPU_37XX_HOST_IF_TBU_MMUSSIDV_TBU4_AWMMUSSIDV_MASK             BIT_MASK(8)
 #define VPU_37XX_HOST_IF_TBU_MMUSSIDV_TBU4_ARMMUSSIDV_MASK             BIT_MASK(9)
 
-#define VPU_37XX_CPU_SS_DSU_LEON_RT_BASE                                       0x04000000u
+#define VPU_37XX_CPU_SS_DSU_LEON_RT_BASE                               0x04000000u
 #define VPU_37XX_CPU_SS_DSU_LEON_RT_DSU_CTRL                           0x04000000u
 #define VPU_37XX_CPU_SS_DSU_LEON_RT_PC_REG                             0x04400010u
 #define VPU_37XX_CPU_SS_DSU_LEON_RT_NPC_REG                            0x04400014u
-#define VPU_37XX_CPU_SS_DSU_LEON_RT_DSU_TRAP_REG                               0x04400020u
+#define VPU_37XX_CPU_SS_DSU_LEON_RT_DSU_TRAP_REG                       0x04400020u
 
 #define VPU_37XX_CPU_SS_MSSCPU_CPR_CLK_SET                             0x06010004u
 #define VPU_37XX_CPU_SS_MSSCPU_CPR_CLK_SET_CPU_DSU_MASK                        BIT_MASK(1)
@@ -259,15 +259,15 @@
 #define VPU_37XX_CPU_SS_MSSCPU_CPR_RST_CLR_CPU_DSU_MASK                        BIT_MASK(1)
 
 #define VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC                         0x06010040u
-#define VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC_IRQI_RSTRUN0_MASK               BIT_MASK(0)
-#define VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC_IRQI_RESUME0_MASK               BIT_MASK(1)
-#define VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC_IRQI_RSTRUN1_MASK               BIT_MASK(2)
-#define VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC_IRQI_RESUME1_MASK               BIT_MASK(3)
+#define VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC_IRQI_RSTRUN0_MASK       BIT_MASK(0)
+#define VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC_IRQI_RESUME0_MASK       BIT_MASK(1)
+#define VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC_IRQI_RSTRUN1_MASK       BIT_MASK(2)
+#define VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC_IRQI_RESUME1_MASK       BIT_MASK(3)
 #define VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC_IRQI_RSTVEC_MASK                GENMASK(31, 4)
 
 #define VPU_37XX_CPU_SS_TIM_WATCHDOG                                   0x0602009cu
 #define VPU_37XX_CPU_SS_TIM_WDOG_EN                                    0x060200a4u
-#define VPU_37XX_CPU_SS_TIM_SAFE                                               0x060200a8u
+#define VPU_37XX_CPU_SS_TIM_SAFE                                       0x060200a8u
 #define VPU_37XX_CPU_SS_TIM_IPC_FIFO                                   0x060200f0u
 
 #define VPU_37XX_CPU_SS_TIM_GEN_CONFIG                                 0x06021008u