phy: qcom-qmp: qserdes-txrx-ufs: Add v6 register offsets

The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB,
UFS and PCIE g3x2. Add the new qserdes TX RX but UFS specific offsets
in a dedicated header file.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230117224148.1914627-5-abel.vesa@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
new file mode 100644 (file)
index 0000000..15bcb4b
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+#ifndef QCOM_PHY_QMP_QSERDES_TXRX_UFS_V6_H_
+#define QCOM_PHY_QMP_QSERDES_TXRX_UFS_V6_H_
+
+#define QSERDES_UFS_V6_TX_RES_CODE_LANE_TX                     0x28
+#define QSERDES_UFS_V6_TX_RES_CODE_LANE_RX                     0x2c
+#define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX              0x30
+#define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX              0x34
+
+#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2          0x08
+#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4          0x10
+#define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL                      0x178
+#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0                     0x208
+#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1                     0x20c
+#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3                     0x214
+#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B6                     0x220
+#define QSERDES_UFS_V6_RX_MODE_RATE2_B3                                0x238
+#define QSERDES_UFS_V6_RX_MODE_RATE2_B6                                0x244
+#define QSERDES_UFS_V6_RX_MODE_RATE3_B3                                0x25c
+#define QSERDES_UFS_V6_RX_MODE_RATE3_B4                                0x260
+#define QSERDES_UFS_V6_RX_MODE_RATE3_B5                                0x264
+#define QSERDES_UFS_V6_RX_MODE_RATE3_B8                                0x270
+#define QSERDES_UFS_V6_RX_MODE_RATE4_B3                                0x280
+#define QSERDES_UFS_V6_RX_MODE_RATE4_B6                                0x28c
+
+#endif

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
index b66a7d1c2e99e5c9a115f45e79d2cfe3d80f0cc9..12ce7138f8efe03f755f60d99e78f8a974830d7c 100644 (file)
--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
@@ -27,6 +27,8 @@
 #include "phy-qcom-qmp-pcs-ufs-v4.h"
 #include "phy-qcom-qmp-pcs-ufs-v5.h"
 
+#include "phy-qcom-qmp-qserdes-txrx-ufs-v6.h"
+
 /* QPHY_SW_RESET bit */
 #define SW_RESET                               BIT(0)
 /* QPHY_POWER_DOWN_CONTROL */