drm/radeon: Replace numbers with PCI_EXP_LNKCTL2 definitions

Replace hard-coded magic numbers with the descriptive PCI_EXP_LNKCTL2
definitions.  No functional change intended.

Link: https://lore.kernel.org/r/20191112173503.176611-4-helgaas@kernel.org
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index 14cdfdf78bde453d1e41463662ec17fb61430367..a280442c81aacc3e19babe9561b96c7230bb44ae 100644 (file)
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -9619,13 +9619,19 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev)
 
                                /* linkctl2 */
                                pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);
-                               tmp16 &= ~((1 << 4) | (7 << 7));
-                               tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 7)));
+                               tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |
+                                          PCI_EXP_LNKCTL2_TX_MARGIN);
+                               tmp16 |= (bridge_cfg2 &
+                                         (PCI_EXP_LNKCTL2_ENTER_COMP |
+                                          PCI_EXP_LNKCTL2_TX_MARGIN));
                                pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);
 
                                pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
-                               tmp16 &= ~((1 << 4) | (7 << 7));
-                               tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 7)));
+                               tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |
+                                          PCI_EXP_LNKCTL2_TX_MARGIN);
+                               tmp16 |= (gpu_cfg2 &
+                                         (PCI_EXP_LNKCTL2_ENTER_COMP |
+                                          PCI_EXP_LNKCTL2_TX_MARGIN));
                                pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
 
                                tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
@@ -9641,13 +9647,13 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev)
        WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
 
        pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
-       tmp16 &= ~0xf;
+       tmp16 &= ~PCI_EXP_LNKCTL2_TLS;
        if (speed_cap == PCIE_SPEED_8_0GT)
-               tmp16 |= 3; /* gen3 */
+               tmp16 |= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */
        else if (speed_cap == PCIE_SPEED_5_0GT)
-               tmp16 |= 2; /* gen2 */
+               tmp16 |= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 */
        else
-               tmp16 |= 1; /* gen1 */
+               tmp16 |= PCI_EXP_LNKCTL2_TLS_2_5GT; /* gen1 */
        pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
 
        speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);

diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 9b7042d3ef1bdd69c884a0222ef7020ea239e611..529e70a42019361859a29f96c76238641a10888a 100644 (file)
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -7202,13 +7202,19 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev)
 
                                /* linkctl2 */
                                pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);
-                               tmp16 &= ~((1 << 4) | (7 << 7));
-                               tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 7)));
+                               tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |
+                                          PCI_EXP_LNKCTL2_TX_MARGIN);
+                               tmp16 |= (bridge_cfg2 &
+                                         (PCI_EXP_LNKCTL2_ENTER_COMP |
+                                          PCI_EXP_LNKCTL2_TX_MARGIN));
                                pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);
 
                                pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
-                               tmp16 &= ~((1 << 4) | (7 << 7));
-                               tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 7)));
+                               tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |
+                                          PCI_EXP_LNKCTL2_TX_MARGIN);
+                               tmp16 |= (gpu_cfg2 &
+                                         (PCI_EXP_LNKCTL2_ENTER_COMP |
+                                          PCI_EXP_LNKCTL2_TX_MARGIN));
                                pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
 
                                tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
@@ -7224,13 +7230,13 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev)
        WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
 
        pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
-       tmp16 &= ~0xf;
+       tmp16 &= ~PCI_EXP_LNKCTL2_TLS;
        if (speed_cap == PCIE_SPEED_8_0GT)
-               tmp16 |= 3; /* gen3 */
+               tmp16 |= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */
        else if (speed_cap == PCIE_SPEED_5_0GT)
-               tmp16 |= 2; /* gen2 */
+               tmp16 |= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 */
        else
-               tmp16 |= 1; /* gen1 */
+               tmp16 |= PCI_EXP_LNKCTL2_TLS_2_5GT; /* gen1 */
        pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
 
        speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);