drm/amdgpu: Optimize xxx_ras_late_init function of each ras block
authoryipechai <YiPeng.Chai@amd.com>
Mon, 14 Feb 2022 06:38:02 +0000 (14:38 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 17 Feb 2022 20:59:05 +0000 (15:59 -0500)
1. Move calling ras block instance members from module internal
   function to the top calling xxx_ras_late_init.
2. Module internal function calls can only use parameter variables
   of xxx_ras_late_init instead of ras block instance members.

Signed-off-by: yipechai <YiPeng.Chai@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.c
drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
drivers/gpu/drm/amd/amdgpu/soc15.c

index b7470ed7bc25f64f1967151f3373a55cf7e73fea..52912b6bcb20d23bda52c74aa978b5c6b87d6f59 100644 (file)
@@ -625,11 +625,11 @@ int amdgpu_get_gfx_off_status(struct amdgpu_device *adev, uint32_t *value)
 int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)
 {
        int r;
-       r = amdgpu_ras_block_late_init(adev, adev->gfx.ras_if);
+       r = amdgpu_ras_block_late_init(adev, ras_block);
        if (r)
                return r;
 
-       if (amdgpu_ras_is_supported(adev, adev->gfx.ras_if->block)) {
+       if (amdgpu_ras_is_supported(adev, ras_block->block)) {
                if (!amdgpu_persistent_edc_harvesting_supported(adev))
                        amdgpu_ras_reset_error_status(adev, AMDGPU_RAS_BLOCK__GFX);
 
@@ -640,7 +640,7 @@ int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *r
 
        return 0;
 late_fini:
-       amdgpu_ras_block_late_fini(adev, adev->gfx.ras_if);
+       amdgpu_ras_block_late_fini(adev, ras_block);
        return r;
 }
 
index dca1dc5b993ccaa17ef2f4c4501fd5d6ccccf196..7bc68c94e0b8dadf7c001bfd0607a0faca152c48 100644 (file)
@@ -452,7 +452,7 @@ int amdgpu_gmc_ras_late_init(struct amdgpu_device *adev)
        int r;
 
        if (adev->umc.ras && adev->umc.ras->ras_block.ras_late_init) {
-               r = adev->umc.ras->ras_block.ras_late_init(adev, NULL);
+               r = adev->umc.ras->ras_block.ras_late_init(adev, adev->umc.ras_if);
                if (r)
                        return r;
        }
@@ -464,7 +464,7 @@ int amdgpu_gmc_ras_late_init(struct amdgpu_device *adev)
        }
 
        if (adev->gmc.xgmi.ras && adev->gmc.xgmi.ras->ras_block.ras_late_init) {
-               r = adev->gmc.xgmi.ras->ras_block.ras_late_init(adev, NULL);
+               r = adev->gmc.xgmi.ras->ras_block.ras_late_init(adev, adev->gmc.xgmi.ras_if);
                if (r)
                        return r;
        }
index 92fd4ffa77793af2a923441d99cedf0aee548842..f09ad80f077263ce722cbab76d31c82a8c265b2a 100644 (file)
 int amdgpu_nbio_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)
 {
        int r;
-       r = amdgpu_ras_block_late_init(adev, adev->nbio.ras_if);
+       r = amdgpu_ras_block_late_init(adev, ras_block);
        if (r)
                return r;
 
-       if (amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) {
+       if (amdgpu_ras_is_supported(adev, ras_block->block)) {
                r = amdgpu_irq_get(adev, &adev->nbio.ras_controller_irq, 0);
                if (r)
                        goto late_fini;
@@ -40,7 +40,7 @@ int amdgpu_nbio_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *
 
        return 0;
 late_fini:
-       amdgpu_ras_block_late_fini(adev, adev->nbio.ras_if);
+       amdgpu_ras_block_late_fini(adev, ras_block);
        return r;
 }
 
index 594454dba4c12b490322bbdb39d7d443c02c7ad2..3b5c43575aa3e98697b8442b0174854b00709815 100644 (file)
@@ -91,11 +91,11 @@ int amdgpu_sdma_ras_late_init(struct amdgpu_device *adev,
 {
        int r, i;
 
-       r = amdgpu_ras_block_late_init(adev, adev->sdma.ras_if);
+       r = amdgpu_ras_block_late_init(adev, ras_block);
        if (r)
                return r;
 
-       if (amdgpu_ras_is_supported(adev, adev->sdma.ras_if->block)) {
+       if (amdgpu_ras_is_supported(adev, ras_block->block)) {
                for (i = 0; i < adev->sdma.num_instances; i++) {
                        r = amdgpu_irq_get(adev, &adev->sdma.ecc_irq,
                                AMDGPU_SDMA_IRQ_INSTANCE0 + i);
@@ -107,7 +107,7 @@ int amdgpu_sdma_ras_late_init(struct amdgpu_device *adev,
        return 0;
 
 late_fini:
-       amdgpu_ras_block_late_fini(adev, adev->sdma.ras_if);
+       amdgpu_ras_block_late_fini(adev, ras_block);
        return r;
 }
 
index 7abf9299e0d7f79fe4362facacd5dc4e289be2a6..9400260e3263e24264ec29268604d2ce6a0c9561 100644 (file)
@@ -140,11 +140,11 @@ int amdgpu_umc_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *r
 {
        int r;
 
-       r = amdgpu_ras_block_late_init(adev, adev->umc.ras_if);
+       r = amdgpu_ras_block_late_init(adev, ras_block);
        if (r)
                return r;
 
-       if (amdgpu_ras_is_supported(adev, adev->umc.ras_if->block)) {
+       if (amdgpu_ras_is_supported(adev, ras_block->block)) {
                r = amdgpu_irq_get(adev, &adev->gmc.ecc_irq, 0);
                if (r)
                        goto late_fini;
@@ -158,7 +158,7 @@ int amdgpu_umc_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *r
        return 0;
 
 late_fini:
-       amdgpu_ras_block_late_fini(adev, adev->umc.ras_if);
+       amdgpu_ras_block_late_fini(adev, ras_block);
        return r;
 }
 
index 91f788f6f6b56f461811d554882d7b8bfdd922dc..77b65434ccc2fe73c8bea4d7da27014460a46962 100644 (file)
@@ -740,7 +740,7 @@ static int amdgpu_xgmi_ras_late_init(struct amdgpu_device *adev, struct ras_comm
 
        adev->gmc.xgmi.ras->ras_block.hw_ops->reset_ras_error_count(adev);
 
-       return amdgpu_ras_block_late_init(adev, adev->gmc.xgmi.ras_if);
+       return amdgpu_ras_block_late_init(adev, ras_block);
 }
 
 static void amdgpu_xgmi_ras_fini(struct amdgpu_device *adev)
index 7e57b90d5b504bef3f6c1829bd89a7b94855205a..bb40ab83fc22da367100fcdf0303f9330b40811e 100644 (file)
@@ -4792,7 +4792,7 @@ static int gfx_v9_0_ecc_late_init(void *handle)
                return r;
 
        if (adev->gfx.ras && adev->gfx.ras->ras_block.ras_late_init) {
-               r = adev->gfx.ras->ras_block.ras_late_init(adev, NULL);
+               r = adev->gfx.ras->ras_block.ras_late_init(adev, adev->gfx.ras_if);
                if (r)
                        return r;
        }
index 82f6b31a19044774d4c5be86cd8b303f5ef58f2f..af5a1c93861b75935b5420419aeaa947357a93f5 100644 (file)
@@ -1895,7 +1895,7 @@ static int sdma_v4_0_late_init(void *handle)
        }
 
        if (adev->sdma.ras && adev->sdma.ras->ras_block.ras_late_init)
-               return adev->sdma.ras->ras_block.ras_late_init(adev, NULL);
+               return adev->sdma.ras->ras_block.ras_late_init(adev, adev->sdma.ras_if);
        else
                return 0;
 }
index a216e625c89ce7291e12e2894c4387dd97aee1c6..99a88f4d8050a87fb4fc0be48e863be584a3edef 100644 (file)
@@ -1195,7 +1195,7 @@ static int soc15_common_late_init(void *handle)
                xgpu_ai_mailbox_get_irq(adev);
 
        if (adev->nbio.ras && adev->nbio.ras->ras_block.ras_late_init)
-               r = adev->nbio.ras->ras_block.ras_late_init(adev, NULL);
+               r = adev->nbio.ras->ras_block.ras_late_init(adev, adev->nbio.ras_if);
 
        return r;
 }