drm/xe/guc: Use valid scratch register for posting read

There are only 4 scratch registers VF_SW_FLAG(0..3) on each GuC.
We shouldn't use non-existing register VF_SW_FLAG(4) for posting
read.

Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
index 56edcb2b0e45234a92182ab9b218a8878bf48e7b..6de2ab05bf4e125f166411b2be605304304c5d38 100644 (file)
--- a/drivers/gpu/drm/xe/xe_guc.c
+++ b/drivers/gpu/drm/xe/xe_guc.c
@@ -615,7 +615,7 @@ int xe_guc_mmio_send_recv(struct xe_guc *guc, const u32 *request,
        u32 header, reply;
        struct xe_reg reply_reg = xe_gt_is_media_type(gt) ?
                MED_VF_SW_FLAG(0) : VF_SW_FLAG(0);
-       const u32 LAST_INDEX = VF_SW_FLAG_COUNT;
+       const u32 LAST_INDEX = VF_SW_FLAG_COUNT - 1;
        int ret;
        int i;