If an interrupt rises during hibernation process, dwc2 will assert
interrupt line to interrupt controller. If interrupt is level
sensitive, interrupt handler will be called in a loop because dwc2
will not be able to clear it while controller is hibernated.
Thus, clear all controller interrupts before hibernation entry.
Signed-off-by: Gregory Herrero <gregory.herrero@intel.com>
Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@intel.com>
Tested-by: Robert Baldyga <r.baldyga@samsung.com>
Tested-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Tested-by: John Youn <johnyoun@synopsys.com>
Acked-by: John Youn <johnyoun@synopsys.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
                }
        }
 
+       /*
+        * Clear any pending interrupts since dwc2 will not be able to
+        * clear them after entering hibernation.
+        */
+       dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
+
        /* Put the controller in low power state */
        pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);