mtd: rawnand: qcom: set BAM mode only if not set already

BAM is DMA controller on QCOM ipq platforms, BAM mode on NAND driver
is set by writing BAM_MODE_EN bit on NAND_CTRL register.

NAND_CTRL is an operational register and in BAM mode operational
registers are read only.

So, before enabling BAM mode by writing the NAND_CTRL register, check
if BAM mode was already enabled by the bootloader, and enable BAM mode
only if it is not enabled already.

Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/1591948696-16015-3-git-send-email-sivaprak@codeaurora.org

diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c
index 78b5f211598c98f44d2736ce0d25bfddbd1249de..bd7a7251429bd91c5e59eea53034ef893114a307 100644 (file)
--- a/drivers/mtd/nand/raw/qcom_nandc.c
+++ b/drivers/mtd/nand/raw/qcom_nandc.c
@@ -2784,7 +2784,16 @@ static int qcom_nandc_setup(struct qcom_nand_controller *nandc)
        /* enable ADM or BAM DMA */
        if (nandc->props->is_bam) {
                nand_ctrl = nandc_read(nandc, NAND_CTRL);
-               nandc_write(nandc, NAND_CTRL, nand_ctrl | BAM_MODE_EN);
+
+               /*
+                *NAND_CTRL is an operational registers, and CPU
+                * access to operational registers are read only
+                * in BAM mode. So update the NAND_CTRL register
+                * only if it is not in BAM mode. In most cases BAM
+                * mode will be enabled in bootloader
+                */
+               if (!(nand_ctrl & BAM_MODE_EN))
+                       nandc_write(nandc, NAND_CTRL, nand_ctrl | BAM_MODE_EN);
        } else {
                nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
        }