void kvm_vgic_init_cpu_hardware(void);
 
 int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int intid,
-                       bool level);
-int kvm_vgic_inject_mapped_irq(struct kvm *kvm, int cpuid, unsigned int intid,
-                              bool level);
+                       bool level, void *owner);
 int kvm_vgic_map_phys_irq(struct kvm_vcpu *vcpu, u32 virt_irq, u32 phys_irq);
 int kvm_vgic_unmap_phys_irq(struct kvm_vcpu *vcpu, unsigned int virt_irq);
 bool kvm_vgic_map_is_active(struct kvm_vcpu *vcpu, unsigned int virt_irq);
 
        if (likely(irqchip_in_kernel(vcpu->kvm))) {
                ret = kvm_vgic_inject_irq(vcpu->kvm, vcpu->vcpu_id,
                                          timer_ctx->irq.irq,
-                                         timer_ctx->irq.level);
+                                         timer_ctx->irq.level,
+                                         timer_ctx);
                WARN_ON(ret);
        }
 }
 
                if (irq_num < VGIC_NR_SGIS || irq_num >= VGIC_NR_PRIVATE_IRQS)
                        return -EINVAL;
 
-               return kvm_vgic_inject_irq(kvm, vcpu->vcpu_id, irq_num, level);
+               return kvm_vgic_inject_irq(kvm, vcpu->vcpu_id, irq_num, level, NULL);
        case KVM_ARM_IRQ_TYPE_SPI:
                if (!irqchip_in_kernel(kvm))
                        return -ENXIO;
                if (irq_num < VGIC_NR_PRIVATE_IRQS)
                        return -EINVAL;
 
-               return kvm_vgic_inject_irq(kvm, 0, irq_num, level);
+               return kvm_vgic_inject_irq(kvm, 0, irq_num, level, NULL);
        }
 
        return -EINVAL;
 
 
        if (likely(irqchip_in_kernel(vcpu->kvm))) {
                int ret = kvm_vgic_inject_irq(vcpu->kvm, vcpu->vcpu_id,
-                                             pmu->irq_num, overflow);
+                                             pmu->irq_num, overflow,
+                                             &vcpu->arch.pmu);
                WARN_ON(ret);
        }
 }
 
 
        if (!vgic_valid_spi(kvm, spi_id))
                return -EINVAL;
-       return kvm_vgic_inject_irq(kvm, 0, spi_id, level);
+       return kvm_vgic_inject_irq(kvm, 0, spi_id, level, NULL);
 }
 
 /**
 
 
 /*
  * Only valid injection if changing level for level-triggered IRQs or for a
- * rising edge.
+ * rising edge, and in-kernel connected IRQ lines can only be controlled by
+ * their owner.
  */
-static bool vgic_validate_injection(struct vgic_irq *irq, bool level)
+static bool vgic_validate_injection(struct vgic_irq *irq, bool level, void *owner)
 {
+       if (irq->owner != owner)
+               return false;
+
        switch (irq->config) {
        case VGIC_CONFIG_LEVEL:
                return irq->line_level != level;
  *                           false: to ignore the call
  *          Level-sensitive  true:  raise the input signal
  *                           false: lower the input signal
+ * @owner:   The opaque pointer to the owner of the IRQ being raised to verify
+ *           that the caller is allowed to inject this IRQ.  Userspace
+ *           injections will have owner == NULL.
  *
  * The VGIC is not concerned with devices being active-LOW or active-HIGH for
  * level-sensitive interrupts.  You can think of the level parameter as 1
  * being HIGH and 0 being LOW and all devices being active-HIGH.
  */
 int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int intid,
-                       bool level)
+                       bool level, void *owner)
 {
        struct kvm_vcpu *vcpu;
        struct vgic_irq *irq;
 
        spin_lock(&irq->irq_lock);
 
-       if (!vgic_validate_injection(irq, level)) {
+       if (!vgic_validate_injection(irq, level, owner)) {
                /* Nothing to see here, move along... */
                spin_unlock(&irq->irq_lock);
                vgic_put_irq(kvm, irq);