clk: qcom: gpucc-sdm845: fix clk_dis_wait being programmed for CX GDSC

The gdsc_init() function will rewrite the CLK_DIS_WAIT field while
registering the GDSC (writing the value 0x2 by default). This will
override the setting done in the driver's probe function.

Set cx_gdsc.clk_dis_wait_val to 8 to follow the intention of the probe
function.

Fixes: 453361cdd757 ("clk: qcom: Add graphics clock controller driver for SDM845")
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230201172305.993146-2-dmitry.baryshkov@linaro.org

diff --git a/drivers/clk/qcom/gpucc-sdm845.c b/drivers/clk/qcom/gpucc-sdm845.c
index 622a54a67d325cc2a5a7253a49a2421d81c62b90..d48ad19e832d356d4919bf0b30f85a752356bec2 100644 (file)
--- a/drivers/clk/qcom/gpucc-sdm845.c
+++ b/drivers/clk/qcom/gpucc-sdm845.c
@@ -22,8 +22,6 @@
 #define CX_GMU_CBCR_SLEEP_SHIFT                4
 #define CX_GMU_CBCR_WAKE_MASK          0xf
 #define CX_GMU_CBCR_WAKE_SHIFT         8
-#define CLK_DIS_WAIT_SHIFT             12
-#define CLK_DIS_WAIT_MASK              (0xf << CLK_DIS_WAIT_SHIFT)
 
 enum {
        P_BI_TCXO,
@@ -121,6 +119,7 @@ static struct clk_branch gpu_cc_cxo_clk = {
 static struct gdsc gpu_cx_gdsc = {
        .gdscr = 0x106c,
        .gds_hw_ctrl = 0x1540,
+       .clk_dis_wait_val = 0x8,
        .pd = {
                .name = "gpu_cx_gdsc",
        },
@@ -193,10 +192,6 @@ static int gpu_cc_sdm845_probe(struct platform_device *pdev)
        value = 0xf << CX_GMU_CBCR_WAKE_SHIFT | 0xf << CX_GMU_CBCR_SLEEP_SHIFT;
        regmap_update_bits(regmap, 0x1098, mask, value);
 
-       /* Configure clk_dis_wait for gpu_cx_gdsc */
-       regmap_update_bits(regmap, 0x106c, CLK_DIS_WAIT_MASK,
-                                               8 << CLK_DIS_WAIT_SHIFT);
-
        return qcom_cc_really_probe(pdev, &gpu_cc_sdm845_desc, regmap);
 }