drm/amd/display: always apply T7/T9 delay logic

[why]
before we exit early in edp_reciever_ready if we detect that panel
is not edp or below rev 1.2. This will skip the backlight/t7 delay panel
patch.

[how]
edit logic to ensure panel patch is applied regardless of edp rev.

Signed-off-by: Martin Leung <martin.leung@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
index ddb8550457672bc57408cdf4835a2cf98d8aea96..58634f191a55d4406f5ddc41b18b9fbd7ec06b6e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
@@ -153,18 +153,19 @@ bool edp_receiver_ready_T9(struct dc_link *link)
        unsigned char edpRev = 0;
        enum dc_status result = DC_OK;
        result = core_link_read_dpcd(link, DP_EDP_DPCD_REV, &edpRev, sizeof(edpRev));
-       if (edpRev < DP_EDP_12)
-               return true;
-       /* start from eDP version 1.2, SINK_STAUS indicate the sink is ready.*/
-       do {
-               sinkstatus = 1;
-               result = core_link_read_dpcd(link, DP_SINK_STATUS, &sinkstatus, sizeof(sinkstatus));
-               if (sinkstatus == 0)
-                       break;
-               if (result != DC_OK)
-                       break;
-               udelay(100); //MAx T9
-       } while (++tries < 50);
+
+     /* start from eDP version 1.2, SINK_STAUS indicate the sink is ready.*/
+       if (result == DC_OK && edpRev >= DP_EDP_12) {
+               do {
+                       sinkstatus = 1;
+                       result = core_link_read_dpcd(link, DP_SINK_STATUS, &sinkstatus, sizeof(sinkstatus));
+                       if (sinkstatus == 0)
+                               break;
+                       if (result != DC_OK)
+                               break;
+                       udelay(100); //MAx T9
+               } while (++tries < 50);
+       }
 
        if (link->local_sink->edid_caps.panel_patch.extra_delay_backlight_off > 0)
                udelay(link->local_sink->edid_caps.panel_patch.extra_delay_backlight_off * 1000);
@@ -183,21 +184,22 @@ bool edp_receiver_ready_T7(struct dc_link *link)
        unsigned long long time_taken_in_ns = 0;
 
        result = core_link_read_dpcd(link, DP_EDP_DPCD_REV, &edpRev, sizeof(edpRev));
-       if (result == DC_OK && edpRev < DP_EDP_12)
-               return true;
-       /* start from eDP version 1.2, SINK_STAUS indicate the sink is ready.*/
-       enter_timestamp = dm_get_timestamp(link->ctx);
-       do {
-               sinkstatus = 0;
-               result = core_link_read_dpcd(link, DP_SINK_STATUS, &sinkstatus, sizeof(sinkstatus));
-               if (sinkstatus == 1)
-                       break;
-               if (result != DC_OK)
-                       break;
-               udelay(25);
-               finish_timestamp = dm_get_timestamp(link->ctx);
-               time_taken_in_ns = dm_get_elapse_time_in_ns(link->ctx, finish_timestamp, enter_timestamp);
-       } while (time_taken_in_ns < 50 * 1000000); //MAx T7 is 50ms
+
+       if (result == DC_OK && edpRev >= DP_EDP_12) {
+               /* start from eDP version 1.2, SINK_STAUS indicate the sink is ready.*/
+               enter_timestamp = dm_get_timestamp(link->ctx);
+               do {
+                       sinkstatus = 0;
+                       result = core_link_read_dpcd(link, DP_SINK_STATUS, &sinkstatus, sizeof(sinkstatus));
+                       if (sinkstatus == 1)
+                               break;
+                       if (result != DC_OK)
+                               break;
+                       udelay(25);
+                       finish_timestamp = dm_get_timestamp(link->ctx);
+                       time_taken_in_ns = dm_get_elapse_time_in_ns(link->ctx, finish_timestamp, enter_timestamp);
+               } while (time_taken_in_ns < 50 * 1000000); //MAx T7 is 50ms
+       }
 
        if (link->local_sink->edid_caps.panel_patch.extra_t7_ms > 0)
                udelay(link->local_sink->edid_caps.panel_patch.extra_t7_ms * 1000);