arm64: dts: qcom: sdm845: add UFS controller

Add the UFS controller and PHY to SDM845.

Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Evan Green <evgreen@chromium.org>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
[bjorn: Add iommu context for the host controller]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>

diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 0f3d84af949d87557b8e4b2f50193340eccc3d9a..d92dd49ed2c385b580c24e90d39a36630d11766b 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -981,6 +981,72 @@
                        };
                };
 
+               ufs_mem_hc: ufshc@1d84000 {
+                       compatible = "qcom,sdm845-ufshc", "qcom,ufshc",
+                                    "jedec,ufs-2.0";
+                       reg = <0x1d84000 0x2500>;
+                       interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
+                       phys = <&ufs_mem_phy_lanes>;
+                       phy-names = "ufsphy";
+                       lanes-per-direction = <2>;
+                       power-domains = <&gcc UFS_PHY_GDSC>;
+
+                       iommus = <&apps_smmu 0x100 0xf>;
+
+                       clock-names =
+                               "core_clk",
+                               "bus_aggr_clk",
+                               "iface_clk",
+                               "core_clk_unipro",
+                               "ref_clk",
+                               "tx_lane0_sync_clk",
+                               "rx_lane0_sync_clk",
+                               "rx_lane1_sync_clk";
+                       clocks =
+                               <&gcc GCC_UFS_PHY_AXI_CLK>,
+                               <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+                               <&gcc GCC_UFS_PHY_AHB_CLK>,
+                               <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
+                               <&rpmhcc RPMH_CXO_CLK>,
+                               <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
+                               <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
+                               <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
+                       freq-table-hz =
+                               <50000000 200000000>,
+                               <0 0>,
+                               <0 0>,
+                               <37500000 150000000>,
+                               <0 0>,
+                               <0 0>,
+                               <0 0>,
+                               <0 0>;
+
+                       status = "disabled";
+               };
+
+               ufs_mem_phy: phy@1d87000 {
+                       compatible = "qcom,sdm845-qmp-ufs-phy";
+                       reg = <0x1d87000 0x18c>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges;
+                       clock-names = "ref",
+                                     "ref_aux";
+                       clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
+                                <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
+
+                       status = "disabled";
+
+                       ufs_mem_phy_lanes: lanes@1d87400 {
+                               reg = <0x1d87400 0x108>,
+                                     <0x1d87600 0x1e0>,
+                                     <0x1d87c00 0x1dc>,
+                                     <0x1d87800 0x108>,
+                                     <0x1d87a00 0x1e0>;
+                               #phy-cells = <0>;
+                       };
+               };
+
                tcsr_mutex_regs: syscon@1f40000 {
                        compatible = "syscon";
                        reg = <0x1f40000 0x40000>;