clk: ti: Fix missing omap4 mcbsp functional clock and aliases
authorTony Lindgren <tony@atomide.com>
Wed, 11 Oct 2023 07:15:56 +0000 (10:15 +0300)
committerTony Lindgren <tony@atomide.com>
Fri, 13 Oct 2023 08:01:48 +0000 (11:01 +0300)
We are using a wrong mcbsp functional clock. The interconnect target module
driver provided clock for mcbsp is not same as the mcbsp functional clock
known as the gfclk main_clk. The mcbsp functional clocks for mcbsp should
have been added before we dropped the legacy platform data.

Additionally we are also missing the clock aliases for the clocks used by
the audio driver if reparenting is needed. This causes audio driver errors
like "CLKS: could not clk_get() prcm_fck" for mcbsp as reported by Andreas.
The mcbsp clock aliases too should have been added before we dropped the
legacy platform data.

Let's add the clocks and aliases with a single patch to fix the issue.

Fixes: 349355ce3a05 ("ARM: OMAP2+: Drop legacy platform data for omap4 mcbsp")
Reported-by: Andreas Kemnade <andreas@kemnade.info>
Reported-by: Péter Ujfalusi <peter.ujfalusi@gmail.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
arch/arm/boot/dts/ti/omap/omap4-l4-abe.dtsi
arch/arm/boot/dts/ti/omap/omap4-l4.dtsi
drivers/clk/ti/clk-44xx.c

index 7ae8b620515c5418140f9e779df2e46031f9dace..59f546a278f87c013e8cbb74ba6dd8607e65ddcb 100644 (file)
                                reg = <0x0 0xff>, /* MPU private access */
                                      <0x49022000 0xff>; /* L3 Interconnect */
                                reg-names = "mpu", "dma";
+                               clocks = <&abe_clkctrl OMAP4_MCBSP1_CLKCTRL 24>;
+                               clock-names = "fck";
                                interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
                                interrupt-names = "common";
                                ti,buffer-size = <128>;
                                reg = <0x0 0xff>, /* MPU private access */
                                      <0x49024000 0xff>; /* L3 Interconnect */
                                reg-names = "mpu", "dma";
+                               clocks = <&abe_clkctrl OMAP4_MCBSP2_CLKCTRL 24>;
+                               clock-names = "fck";
                                interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
                                interrupt-names = "common";
                                ti,buffer-size = <128>;
                                reg = <0x0 0xff>, /* MPU private access */
                                      <0x49026000 0xff>; /* L3 Interconnect */
                                reg-names = "mpu", "dma";
+                               clocks = <&abe_clkctrl OMAP4_MCBSP3_CLKCTRL 24>;
+                               clock-names = "fck";
                                interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
                                interrupt-names = "common";
                                ti,buffer-size = <128>;
index 46b8f9efd41316bde4c2f74473e95e1af3183ffe..3fcef3080eaec8180f245eadc12b2560fc1b4976 100644 (file)
                                compatible = "ti,omap4-mcbsp";
                                reg = <0x0 0xff>; /* L4 Interconnect */
                                reg-names = "mpu";
+                               clocks = <&l4_per_clkctrl OMAP4_MCBSP4_CLKCTRL 24>;
+                               clock-names = "fck";
                                interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
                                interrupt-names = "common";
                                ti,buffer-size = <128>;
index 868bc7af21b0b3482cc235ef5e24cd59ddf107f4..9b2824ed785b995b9d85e485ab5a068bbf911384 100644 (file)
@@ -749,9 +749,14 @@ static struct ti_dt_clk omap44xx_clks[] = {
        DT_CLK(NULL, "mcbsp1_sync_mux_ck", "abe-clkctrl:0028:26"),
        DT_CLK(NULL, "mcbsp2_sync_mux_ck", "abe-clkctrl:0030:26"),
        DT_CLK(NULL, "mcbsp3_sync_mux_ck", "abe-clkctrl:0038:26"),
+       DT_CLK("40122000.mcbsp", "prcm_fck", "abe-clkctrl:0028:26"),
+       DT_CLK("40124000.mcbsp", "prcm_fck", "abe-clkctrl:0030:26"),
+       DT_CLK("40126000.mcbsp", "prcm_fck", "abe-clkctrl:0038:26"),
        DT_CLK(NULL, "mcbsp4_sync_mux_ck", "l4-per-clkctrl:00c0:26"),
+       DT_CLK("48096000.mcbsp", "prcm_fck", "l4-per-clkctrl:00c0:26"),
        DT_CLK(NULL, "ocp2scp_usb_phy_phy_48m", "l3-init-clkctrl:00c0:8"),
        DT_CLK(NULL, "otg_60m_gfclk", "l3-init-clkctrl:0040:24"),
+       DT_CLK(NULL, "pad_fck", "pad_clks_ck"),
        DT_CLK(NULL, "per_mcbsp4_gfclk", "l4-per-clkctrl:00c0:24"),
        DT_CLK(NULL, "pmd_stm_clock_mux_ck", "emu-sys-clkctrl:0000:20"),
        DT_CLK(NULL, "pmd_trace_clk_mux_ck", "emu-sys-clkctrl:0000:22"),