data[4] = down_count * devpriv->clock_ns;
                        return -EAGAIN;
                }
-               ni_writel(dev, MSeries_Cal_PWM_High_Time_Bits(up_count) |
-                              MSeries_Cal_PWM_Low_Time_Bits(down_count),
+               ni_writel(dev, NI_M_CAL_PWM_HIGH_TIME(up_count) |
+                              NI_M_CAL_PWM_LOW_TIME(down_count),
                          NI_M_CAL_PWM_REG);
                devpriv->pwm_up_count = up_count;
                devpriv->pwm_down_count = down_count;
 
 #define NI_M_DIO_REG                   0x024
 #define NI_M_DIO_DIR_REG               0x028
 #define NI_M_CAL_PWM_REG               0x040
+#define NI_M_CAL_PWM_HIGH_TIME(x)      (((x) & 0xffff) << 16)
+#define NI_M_CAL_PWM_LOW_TIME(x)       (((x) & 0xffff) << 0)
 #define NI_M_GEN_PWM_REG(x)            (0x044 + ((x) * 2))
 #define NI_M_AI_CFG_FIFO_DATA_REG      0x05e
 #define NI_M_AI_CFG_LAST_CHAN          BIT(14)
 #define NI_M_AO_REF_ATTENUATION_REG(x) (0x264 + (x))
 #define NI_M_AO_REF_ATTENUATION_X5     BIT(0)
 
-static inline unsigned MSeries_Cal_PWM_High_Time_Bits(unsigned count)
-{
-       return (count << 16) & 0xffff0000;
-}
-
-static inline unsigned MSeries_Cal_PWM_Low_Time_Bits(unsigned count)
-{
-       return count & 0xffff;
-}
-
 static inline unsigned MSeries_PFI_Output_Select_Mask(unsigned channel)
 {
        return 0x1f << (channel % 3) * 5;