net/mlx5: Handle "enable_roce" devlink param
authorMichael Guralnik <michaelgur@mellanox.com>
Fri, 8 Nov 2019 23:45:24 +0000 (23:45 +0000)
committerSaeed Mahameed <saeedm@mellanox.com>
Mon, 11 Nov 2019 20:15:29 +0000 (12:15 -0800)
Register "enable_roce" param, default value is RoCE enabled.
Current configuration is stored on mlx5_core_dev and exposed to user
through the cmode runtime devlink param.
Changing configuration requires changing the cmode driverinit devlink
param and calling devlink reload.

Signed-off-by: Michael Guralnik <michaelgur@mellanox.com>
Acked-by: Jiri Pirko <jiri@mellanox.com>
Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
Documentation/networking/device_drivers/mellanox/mlx5.rst
Documentation/networking/devlink-params-mlx5.txt
drivers/net/ethernet/mellanox/mlx5/core/devlink.c
include/linux/mlx5/driver.h

index d071c6b49e1ff9d7d83bec0c6d722d644554c703..7599dceba9f1bb991fc481b2ab391c6e2c471202 100644 (file)
@@ -154,6 +154,27 @@ User command examples:
       values:
          cmode runtime value smfs
 
+enable_roce: RoCE enablement state
+----------------------------------
+RoCE enablement state controls driver support for RoCE traffic.
+When RoCE is disabled, there is no gid table, only raw ethernet QPs are supported and traffic on the well known UDP RoCE port is handled as raw ethernet traffic.
+
+To change RoCE enablement state a user must change the driverinit cmode value and run devlink reload.
+
+User command examples:
+
+- Disable RoCE::
+
+    $ devlink dev param set pci/0000:06:00.0 name enable_roce value false cmode driverinit
+    $ devlink dev reload pci/0000:06:00.0
+
+- Read RoCE enablement state::
+
+    $ devlink dev param show pci/0000:06:00.0 name enable_roce
+      pci/0000:06:00.0:
+      name enable_roce type generic
+      values:
+         cmode driverinit value true
 
 Devlink health reporters
 ========================
index 8c0b82d655dc2cf992f433042eadb0bf60d8a063..5071467118bd2c9ea79ac9570f4422668b0c578d 100644 (file)
@@ -10,3 +10,8 @@ flow_steering_mode    [DEVICE, DRIVER-SPECIFIC]
                        without firmware intervention.
                        Type: String
                        Configuration mode: runtime
+
+enable_roce            [DEVICE, GENERIC]
+                       Enable handling of RoCE traffic in the device.
+                       Defaultly enabled.
+                       Configuration mode: driverinit
index 381925c90d94ee145528beeb93bfbe2c6745092e..b2c26388edb1c1104deca0c84a33cb4aa5b20a60 100644 (file)
@@ -177,12 +177,29 @@ enum mlx5_devlink_param_id {
        MLX5_DEVLINK_PARAM_FLOW_STEERING_MODE,
 };
 
+static int mlx5_devlink_enable_roce_validate(struct devlink *devlink, u32 id,
+                                            union devlink_param_value val,
+                                            struct netlink_ext_ack *extack)
+{
+       struct mlx5_core_dev *dev = devlink_priv(devlink);
+       bool new_state = val.vbool;
+
+       if (new_state && !MLX5_CAP_GEN(dev, roce)) {
+               NL_SET_ERR_MSG_MOD(extack, "Device doesn't support RoCE");
+               return -EOPNOTSUPP;
+       }
+
+       return 0;
+}
+
 static const struct devlink_param mlx5_devlink_params[] = {
        DEVLINK_PARAM_DRIVER(MLX5_DEVLINK_PARAM_FLOW_STEERING_MODE,
                             "flow_steering_mode", DEVLINK_PARAM_TYPE_STRING,
                             BIT(DEVLINK_PARAM_CMODE_RUNTIME),
                             mlx5_devlink_fs_mode_get, mlx5_devlink_fs_mode_set,
                             mlx5_devlink_fs_mode_validate),
+       DEVLINK_PARAM_GENERIC(ENABLE_ROCE, BIT(DEVLINK_PARAM_CMODE_DRIVERINIT),
+                             NULL, NULL, mlx5_devlink_enable_roce_validate),
 };
 
 static void mlx5_devlink_set_params_init_values(struct devlink *devlink)
@@ -197,6 +214,11 @@ static void mlx5_devlink_set_params_init_values(struct devlink *devlink)
        devlink_param_driverinit_value_set(devlink,
                                           MLX5_DEVLINK_PARAM_FLOW_STEERING_MODE,
                                           value);
+
+       value.vbool = MLX5_CAP_GEN(dev, roce);
+       devlink_param_driverinit_value_set(devlink,
+                                          DEVLINK_PARAM_GENERIC_ID_ENABLE_ROCE,
+                                          value);
 }
 
 int mlx5_devlink_register(struct devlink *devlink, struct device *dev)
index 7b4801e96febc79b429eb2b50c0a7b9d948c42ac..1884513aac90d9bc8b50407cf115f17a65e40ce0 100644 (file)
@@ -1191,4 +1191,15 @@ enum {
        MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
 };
 
+static inline bool mlx5_is_roce_enabled(struct mlx5_core_dev *dev)
+{
+       struct devlink *devlink = priv_to_devlink(dev);
+       union devlink_param_value val;
+
+       devlink_param_driverinit_value_get(devlink,
+                                          DEVLINK_PARAM_GENERIC_ID_ENABLE_ROCE,
+                                          &val);
+       return val.vbool;
+}
+
 #endif /* MLX5_DRIVER_H */