arm64: dts: sc7180: Add sdhc opps and power-domains

Add the power domain supporting performance state and the corresponding
OPP tables for the sdhc device on sc7180.

Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Link: https://lore.kernel.org/r/1593506712-24557-5-git-send-email-rnayak@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 725a47a977cbdaf0cd541c498d03373381559dba..126e2fce26c1a4438cc12269b49d44b751b878e7 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -684,6 +684,8 @@
                        clocks = <&gcc GCC_SDCC1_APPS_CLK>,
                                        <&gcc GCC_SDCC1_AHB_CLK>;
                        clock-names = "core", "iface";
+                       power-domains = <&rpmhpd SC7180_CX>;
+                       operating-points-v2 = <&sdhc1_opp_table>;
 
                        bus-width = <8>;
                        non-removable;
@@ -695,6 +697,20 @@
                        mmc-hs400-enhanced-strobe;
 
                        status = "disabled";
+
+                       sdhc1_opp_table: sdhc1-opp-table {
+                               compatible = "operating-points-v2";
+
+                               opp-100000000 {
+                                       opp-hz = /bits/ 64 <100000000>;
+                                       required-opps = <&rpmhpd_opp_low_svs>;
+                               };
+
+                               opp-384000000 {
+                                       opp-hz = /bits/ 64 <384000000>;
+                                       required-opps = <&rpmhpd_opp_svs_l1>;
+                               };
+                       };
                };
 
                qup_opp_table: qup-opp-table {
@@ -2460,10 +2476,26 @@
                        clocks = <&gcc GCC_SDCC2_APPS_CLK>,
                                        <&gcc GCC_SDCC2_AHB_CLK>;
                        clock-names = "core", "iface";
+                       power-domains = <&rpmhpd SC7180_CX>;
+                       operating-points-v2 = <&sdhc2_opp_table>;
 
                        bus-width = <4>;
 
                        status = "disabled";
+
+                       sdhc2_opp_table: sdhc2-opp-table {
+                               compatible = "operating-points-v2";
+
+                               opp-100000000 {
+                                       opp-hz = /bits/ 64 <100000000>;
+                                       required-opps = <&rpmhpd_opp_low_svs>;
+                               };
+
+                               opp-202000000 {
+                                       opp-hz = /bits/ 64 <202000000>;
+                                       required-opps = <&rpmhpd_opp_svs_l1>;
+                               };
+                       };
                };
 
                qspi_opp_table: qspi-opp-table {