drm/i915: rename DISP_STEPPING->DISPLAY_STEP and GT_STEPPING->GT_STEP

Matter of taste. STEP matches the enums.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/cf2dccd1c9c7fdcf5de08ea10a9265292b45d8c7.1616764798.git.jani.nikula@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index cef177208e6866d750b0bf45b22cac1dfa4f29aa..99126caf5747903d90e5e82ec95d113b2b20a012 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -5333,7 +5333,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
 
        if (IS_ALDERLAKE_S(dev_priv) ||
            IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
-           IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_B0))
+           IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
                /* Wa_1409767108:tgl,dg1,adl-s */
                table = wa_1409767108_buddy_page_masks;
        else

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index d05f9aaa8c06f714e3aa1d71afc2f4cdac9b53d3..1d561812fcad443b0492d5b9dcfa49a993ef6313 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -548,7 +548,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
 
        if (intel_dp->psr.psr2_sel_fetch_enabled) {
                /* WA 1408330847 */
-               if (IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_A0) ||
+               if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) ||
                    IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0))
                        intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
                                     DIS_RAM_BYPASS_PSR2_MAN_TRACK,
@@ -1109,7 +1109,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
 
        /* WA 1408330847 */
        if (intel_dp->psr.psr2_sel_fetch_enabled &&
-           (IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_A0) ||
+           (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) ||
             IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0)))
                intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
                             DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);

diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index c6d7b6c054b56c01e20a3aad4bfc60779dd22852..245c102215387c14dcb66d42f10daa7b3b84d543 100644 (file)
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -1858,7 +1858,7 @@ static bool gen12_plane_supports_mc_ccs(struct drm_i915_private *dev_priv,
 {
        /* Wa_14010477008:tgl[a0..c0],rkl[all],dg1[all] */
        if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv) ||
-           IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_C0))
+           IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0))
                return false;
 
        return plane_id < PLANE_SPRITE4;

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index a6ef97c67d9ab1013742653d30922654cb66d9cf..821142c02ae5f548bf3b14f88d03671623b70308 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1093,19 +1093,19 @@ tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
        gen12_gt_workarounds_init(i915, wal);
 
        /* Wa_1409420604:tgl */
-       if (IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0))
+       if (IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_A0))
                wa_write_or(wal,
                            SUBSLICE_UNIT_LEVEL_CLKGATE2,
                            CPSSUNIT_CLKGATE_DIS);
 
        /* Wa_1607087056:tgl also know as BUG:1409180338 */
-       if (IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0))
+       if (IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_A0))
                wa_write_or(wal,
                            SLICE_UNIT_LEVEL_CLKGATE,
                            L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
 
        /* Wa_1408615072:tgl[a0] */
-       if (IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0))
+       if (IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_A0))
                wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
                            VSUNIT_CLKGATE_DIS_TGL);
 }
@@ -1583,7 +1583,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
        struct drm_i915_private *i915 = engine->i915;
 
        if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
-           IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0)) {
+           IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_A0)) {
                /*
                 * Wa_1607138336:tgl[a0],dg1[a0]
                 * Wa_1607063988:tgl[a0],dg1[a0]
@@ -1593,7 +1593,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
                            GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
        }
 
-       if (IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0)) {
+       if (IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_A0)) {
                /*
                 * Wa_1606679103:tgl
                 * (see also Wa_1606682166:icl)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b300d6f78675c638d54c8d80eb76206518d2878d..1c9cfac0c934c55ed52527b69db597cabbd935e0 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1502,15 +1502,15 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_JSL_EHL_REVID(p, since, until) \
        (IS_JSL_EHL(p) && IS_REVID(p, since, until))
 
-#define IS_TGL_DISP_STEPPING(__i915, since, until) \
+#define IS_TGL_DISPLAY_STEP(__i915, since, until) \
        (IS_TIGERLAKE(__i915) && \
         IS_DISPLAY_STEP(__i915, since, until))
 
-#define IS_TGL_UY_GT_STEPPING(__i915, since, until) \
+#define IS_TGL_UY_GT_STEP(__i915, since, until) \
        ((IS_TGL_U(__i915) || IS_TGL_Y(__i915)) && \
         IS_GT_STEP(__i915, since, until))
 
-#define IS_TGL_GT_STEPPING(__i915, since, until) \
+#define IS_TGL_GT_STEP(__i915, since, until) \
        (IS_TIGERLAKE(__i915) && !(IS_TGL_U(__i915) || IS_TGL_Y(__i915)) && \
         IS_GT_STEP(__i915, since, until))
 
@@ -1527,11 +1527,11 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_DG1_REVID(p, since, until) \
        (IS_DG1(p) && IS_REVID(p, since, until))
 
-#define IS_ADLS_DISP_STEPPING(__i915, since, until) \
+#define IS_ADLS_DISPLAY_STEP(__i915, since, until) \
        (IS_ALDERLAKE_S(__i915) && \
         IS_DISPLAY_STEP(__i915, since, until))
 
-#define IS_ADLS_GT_STEPPING(__i915, since, until) \
+#define IS_ADLS_GT_STEP(__i915, since, until) \
        (IS_ALDERLAKE_S(__i915) && \
         IS_GT_STEP(__i915, since, until))
 

diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 8aaa0f8f6cfd579d933b98b7007d046c282392f6..1035a841610bde86235cf71b039e61f5b2bce6fe 100644 (file)
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -251,7 +251,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
        enum pipe pipe;
 
        /* Wa_14011765242: adl-s A0 */
-       if (IS_ADLS_DISP_STEPPING(dev_priv, STEP_A0, STEP_A0))
+       if (IS_ADLS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
                for_each_pipe(dev_priv, pipe)
                        runtime->num_scalers[pipe] = 0;
        else if (INTEL_GEN(dev_priv) >= 10) {

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index e2dd3140eb0b3436ab179adf2e30cc60351c372e..066abaa73a06f1d70697f5df80ffed2ea7ab7cb6 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7134,7 +7134,7 @@ static void gen12lp_init_clock_gating(struct drm_i915_private *dev_priv)
                           ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);
 
        /* Wa_1409825376:tgl (pre-prod)*/
-       if (IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_B1))
+       if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B1))
                intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_3) |
                           TGL_VRH_GATING_DIS);