#define MMU_FTR_TYPE_40x               ASM_CONST(0x00000004)
 #define MMU_FTR_TYPE_44x               ASM_CONST(0x00000008)
 #define MMU_FTR_TYPE_FSL_E             ASM_CONST(0x00000010)
-#define MMU_FTR_TYPE_3E                        ASM_CONST(0x00000020)
-#define MMU_FTR_TYPE_47x               ASM_CONST(0x00000040)
+#define MMU_FTR_TYPE_47x               ASM_CONST(0x00000020)
 
 /*
  * This is individual features
                                MMU_FTR_CI_LARGE_PAGE
 #define MMU_FTRS_PA6T          MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \
                                MMU_FTR_CI_LARGE_PAGE | MMU_FTR_NO_SLBIE_B
-#define MMU_FTRS_A2            MMU_FTR_TYPE_3E | MMU_FTR_USE_TLBILX | \
-                               MMU_FTR_USE_TLBIVAX_BCAST | \
-                               MMU_FTR_LOCK_BCAST_INVAL | \
-                               MMU_FTR_USE_TLBRSRV | \
-                               MMU_FTR_USE_PAIRED_MAS | \
-                               MMU_FTR_TLBIEL | \
-                               MMU_FTR_16M_PAGE
 #ifndef __ASSEMBLY__
 #include <asm/cputable.h>
 
 
        } else if (mmu_has_feature(MMU_FTR_TYPE_47x)) {
                first_context = 1;
                last_context = 65535;
-       } else
-#ifdef CONFIG_PPC_BOOK3E_MMU
-       if (mmu_has_feature(MMU_FTR_TYPE_3E)) {
-               u32 mmucfg = mfspr(SPRN_MMUCFG);
-               u32 pid_bits = (mmucfg & MMUCFG_PIDSIZE_MASK)
-                               >> MMUCFG_PIDSIZE_SHIFT;
-               first_context = 1;
-               last_context = (1UL << (pid_bits + 1)) - 1;
-       } else
-#endif
-       {
+       } else {
                first_context = 1;
                last_context = 255;
        }