x86/cpu: Add MSR numbers for FRED configuration

Add MSR numbers for the FRED configuration registers per FRED spec 5.0.

Originally-by: Megha Dey <megha.dey@intel.com>
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Signed-off-by: Xin Li <xin3.li@intel.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Tested-by: Shan Kang <shan.kang@intel.com>
Link: https://lore.kernel.org/r/20231205105030.8698-13-xin3.li@intel.com

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index f1bd7b91b3c63735738825f15cd3c82fca7579ce..1f9dc9bd13eb7e9c7bc509b1d09cec7f473157b4 100644 (file)
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -36,8 +36,19 @@
 #define EFER_FFXSR             (1<<_EFER_FFXSR)
 #define EFER_AUTOIBRS          (1<<_EFER_AUTOIBRS)
 
-/* Intel MSRs. Some also available on other CPUs */
+/* FRED MSRs */
+#define MSR_IA32_FRED_RSP0     0x1cc                   /* Level 0 stack pointer */
+#define MSR_IA32_FRED_RSP1     0x1cd                   /* Level 1 stack pointer */
+#define MSR_IA32_FRED_RSP2     0x1ce                   /* Level 2 stack pointer */
+#define MSR_IA32_FRED_RSP3     0x1cf                   /* Level 3 stack pointer */
+#define MSR_IA32_FRED_STKLVLS  0x1d0                   /* Exception stack levels */
+#define MSR_IA32_FRED_SSP0     MSR_IA32_PL0_SSP        /* Level 0 shadow stack pointer */
+#define MSR_IA32_FRED_SSP1     0x1d1                   /* Level 1 shadow stack pointer */
+#define MSR_IA32_FRED_SSP2     0x1d2                   /* Level 2 shadow stack pointer */
+#define MSR_IA32_FRED_SSP3     0x1d3                   /* Level 3 shadow stack pointer */
+#define MSR_IA32_FRED_CONFIG   0x1d4                   /* Entrypoint and interrupt stack level */
 
+/* Intel MSRs. Some also available on other CPUs */
 #define MSR_TEST_CTRL                          0x00000033
 #define MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT    29
 #define MSR_TEST_CTRL_SPLIT_LOCK_DETECT                BIT(MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT)

diff --git a/tools/arch/x86/include/asm/msr-index.h b/tools/arch/x86/include/asm/msr-index.h
index 1d51e1850ed03d46e84c71de0c451067d0baac5b..74f2c63ce717280e54235b92fec0da2d1e4579e8 100644 (file)
--- a/tools/arch/x86/include/asm/msr-index.h
+++ b/tools/arch/x86/include/asm/msr-index.h
@@ -36,8 +36,19 @@
 #define EFER_FFXSR             (1<<_EFER_FFXSR)
 #define EFER_AUTOIBRS          (1<<_EFER_AUTOIBRS)
 
-/* Intel MSRs. Some also available on other CPUs */
+/* FRED MSRs */
+#define MSR_IA32_FRED_RSP0     0x1cc                   /* Level 0 stack pointer */
+#define MSR_IA32_FRED_RSP1     0x1cd                   /* Level 1 stack pointer */
+#define MSR_IA32_FRED_RSP2     0x1ce                   /* Level 2 stack pointer */
+#define MSR_IA32_FRED_RSP3     0x1cf                   /* Level 3 stack pointer */
+#define MSR_IA32_FRED_STKLVLS  0x1d0                   /* Exception stack levels */
+#define MSR_IA32_FRED_SSP0     MSR_IA32_PL0_SSP        /* Level 0 shadow stack pointer */
+#define MSR_IA32_FRED_SSP1     0x1d1                   /* Level 1 shadow stack pointer */
+#define MSR_IA32_FRED_SSP2     0x1d2                   /* Level 2 shadow stack pointer */
+#define MSR_IA32_FRED_SSP3     0x1d3                   /* Level 3 shadow stack pointer */
+#define MSR_IA32_FRED_CONFIG   0x1d4                   /* Entrypoint and interrupt stack level */
 
+/* Intel MSRs. Some also available on other CPUs */
 #define MSR_TEST_CTRL                          0x00000033
 #define MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT    29
 #define MSR_TEST_CTRL_SPLIT_LOCK_DETECT                BIT(MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT)