PCI: rockchip: Use 64-bit mask on MSI 64-bit PCI address
authorRick Wertenbroek <rick.wertenbroek@gmail.com>
Mon, 3 Jul 2023 08:58:45 +0000 (10:58 +0200)
committerKrzysztof Wilczyński <kwilczynski@kernel.org>
Thu, 13 Jul 2023 18:25:44 +0000 (18:25 +0000)
A 32-bit mask was used on the 64-bit PCI address used for mapping MSIs.
This would result in the upper 32 bits being unintentionally zeroed and
MSIs getting mapped to incorrect PCI addresses if the address had any
of the upper bits set.

Replace 32-bit mask by appropriate 64-bit mask.

[kwilczynski: use GENMASK_ULL() over GENMASK() for 32-bit compatibility]
Fixes: dc73ed0f1b8b ("PCI: rockchip: Fix window mapping and address translation for endpoint")
Closes: https://lore.kernel.org/linux-pci/8d19e5b7-8fa0-44a4-90e2-9bb06f5eb694@moroto.mountain
Link: https://lore.kernel.org/linux-pci/20230703085845.2052008-1-rick.wertenbroek@gmail.com
Reported-by: Dan Carpenter <dan.carpenter@linaro.org>
Signed-off-by: Rick Wertenbroek <rick.wertenbroek@gmail.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Damien Le Moal <dlemoal@kernel.org>
Cc: stable@vger.kernel.org
drivers/pci/controller/pcie-rockchip.h

index fe0333778fd93c0a40b0d78f330c7849affb9109..6111de35f84ca2c9f223e9f4b57fc6f42c4f6ee7 100644 (file)
 #define PCIE_RC_CONFIG_THP_CAP         (PCIE_RC_CONFIG_BASE + 0x274)
 #define   PCIE_RC_CONFIG_THP_CAP_NEXT_MASK     GENMASK(31, 20)
 
-#define PCIE_ADDR_MASK                 0xffffff00
+#define MAX_AXI_IB_ROOTPORT_REGION_NUM         3
+#define MIN_AXI_ADDR_BITS_PASSED               8
+#define PCIE_ADDR_MASK                 GENMASK_ULL(63, MIN_AXI_ADDR_BITS_PASSED)
 #define PCIE_CORE_AXI_CONF_BASE                0xc00000
 #define PCIE_CORE_OB_REGION_ADDR0      (PCIE_CORE_AXI_CONF_BASE + 0x0)
 #define   PCIE_CORE_OB_REGION_ADDR0_NUM_BITS   0x3f
 #define AXI_WRAPPER_TYPE1_CFG                  0xb
 #define AXI_WRAPPER_NOR_MSG                    0xc
 
-#define MAX_AXI_IB_ROOTPORT_REGION_NUM         3
-#define MIN_AXI_ADDR_BITS_PASSED               8
 #define PCIE_RC_SEND_PME_OFF                   0x11960
 #define ROCKCHIP_VENDOR_ID                     0x1d87
 #define PCIE_LINK_IS_L2(x) \