drm/amdgpu: remove check for CE in RAS error address query

Only RAS UE error address is queried currently, no need to check CE status.

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
index 939cb203f7ad53de64d2b1245d6d2873971ccdf7..f17d297b594bc0da1385347f7d5301e29eb2d8a0 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
@@ -327,10 +327,9 @@ static void umc_v6_1_query_error_address(struct amdgpu_device *adev,
                return;
        }
 
-       /* calculate error address if ue/ce error is detected */
+       /* calculate error address if ue error is detected */
        if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
-           (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 ||
-           REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)) {
+           REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1) {
 
                err_addr = RREG64_PCIE((mc_umc_addrt0 + umc_reg_offset) * 4);
                /* the lowest lsb bits should be ignored */
@@ -343,10 +342,7 @@ static void umc_v6_1_query_error_address(struct amdgpu_device *adev,
                                ADDR_OF_256B_BLOCK(channel_index) |
                                OFFSET_IN_256B_BLOCK(err_addr);
 
-               /* we only save ue error information currently, ce is skipped */
-               if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC)
-                               == 1)
-                       amdgpu_umc_fill_error_record(err_data, err_addr,
+               amdgpu_umc_fill_error_record(err_data, err_addr,
                                        retired_page, channel_index, umc_inst);
        }
 

diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c b/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c
index a0d19b7683463c6def62ea1771cd2d328577c35d..64d760eb92a3908dca112ab4f567d6e1630e0938 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c
+++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c
@@ -209,10 +209,9 @@ static void umc_v6_7_ecc_info_query_error_address(struct amdgpu_device *adev,
        if (!err_data->err_addr)
                return;
 
-       /* calculate error address if ue/ce error is detected */
+       /* calculate error address if ue error is detected */
        if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
-           (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 ||
-           REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)) {
+           REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1) {
 
                err_addr = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_addr;
                err_addr = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr);
@@ -228,22 +227,18 @@ static void umc_v6_7_ecc_info_query_error_address(struct amdgpu_device *adev,
                /* clear [C4 C3 C2] in soc physical address */
                soc_pa &= ~(0x7ULL << UMC_V6_7_PA_C2_BIT);
 
-               /* we only save ue error information currently, ce is skipped */
-               if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC)
-                               == 1) {
-                       /* loop for all possibilities of [C4 C3 C2] */
-                       for (column = 0; column < UMC_V6_7_NA_MAP_PA_NUM; column++) {
-                               retired_page = soc_pa | (column << UMC_V6_7_PA_C2_BIT);
-                               dev_info(adev->dev, "Error Address(PA): 0x%llx\n", retired_page);
-                               amdgpu_umc_fill_error_record(err_data, err_addr,
-                                       retired_page, channel_index, umc_inst);
-
-                               /* shift R14 bit */
-                               retired_page ^= (0x1ULL << UMC_V6_7_PA_R14_BIT);
-                               dev_info(adev->dev, "Error Address(PA): 0x%llx\n", retired_page);
-                               amdgpu_umc_fill_error_record(err_data, err_addr,
-                                       retired_page, channel_index, umc_inst);
-                       }
+               /* loop for all possibilities of [C4 C3 C2] */
+               for (column = 0; column < UMC_V6_7_NA_MAP_PA_NUM; column++) {
+                       retired_page = soc_pa | (column << UMC_V6_7_PA_C2_BIT);
+                       dev_info(adev->dev, "Error Address(PA): 0x%llx\n", retired_page);
+                       amdgpu_umc_fill_error_record(err_data, err_addr,
+                               retired_page, channel_index, umc_inst);
+
+                       /* shift R14 bit */
+                       retired_page ^= (0x1ULL << UMC_V6_7_PA_R14_BIT);
+                       dev_info(adev->dev, "Error Address(PA): 0x%llx\n", retired_page);
+                       amdgpu_umc_fill_error_record(err_data, err_addr,
+                               retired_page, channel_index, umc_inst);
                }
        }
 }
@@ -481,10 +476,9 @@ static void umc_v6_7_query_error_address(struct amdgpu_device *adev,
        channel_index =
                adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num + ch_inst];
 
-       /* calculate error address if ue/ce error is detected */
+       /* calculate error address if ue error is detected */
        if ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
-           (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 ||
-           REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)) ||
+           REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1) ||
            mca_addr != UMC_INVALID_ADDR) {
                if (mca_addr == UMC_INVALID_ADDR) {
                        err_addr = RREG64_PCIE((mc_umc_addrt0 + umc_reg_offset) * 4);
@@ -505,23 +499,18 @@ static void umc_v6_7_query_error_address(struct amdgpu_device *adev,
                /* clear [C4 C3 C2] in soc physical address */
                soc_pa &= ~(0x7ULL << UMC_V6_7_PA_C2_BIT);
 
-               /* we only save ue error information currently, ce is skipped */
-               if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC)
-                               == 1 ||
-                   mca_addr != UMC_INVALID_ADDR) {
-                       /* loop for all possibilities of [C4 C3 C2] */
-                       for (column = 0; column < UMC_V6_7_NA_MAP_PA_NUM; column++) {
-                               retired_page = soc_pa | (column << UMC_V6_7_PA_C2_BIT);
-                               dev_info(adev->dev, "Error Address(PA): 0x%llx\n", retired_page);
-                               amdgpu_umc_fill_error_record(err_data, err_addr,
-                                       retired_page, channel_index, umc_inst);
-
-                               /* shift R14 bit */
-                               retired_page ^= (0x1ULL << UMC_V6_7_PA_R14_BIT);
-                               dev_info(adev->dev, "Error Address(PA): 0x%llx\n", retired_page);
-                               amdgpu_umc_fill_error_record(err_data, err_addr,
-                                       retired_page, channel_index, umc_inst);
-                       }
+               /* loop for all possibilities of [C4 C3 C2] */
+               for (column = 0; column < UMC_V6_7_NA_MAP_PA_NUM; column++) {
+                       retired_page = soc_pa | (column << UMC_V6_7_PA_C2_BIT);
+                       dev_info(adev->dev, "Error Address(PA): 0x%llx\n", retired_page);
+                       amdgpu_umc_fill_error_record(err_data, err_addr,
+                               retired_page, channel_index, umc_inst);
+
+                       /* shift R14 bit */
+                       retired_page ^= (0x1ULL << UMC_V6_7_PA_R14_BIT);
+                       dev_info(adev->dev, "Error Address(PA): 0x%llx\n", retired_page);
+                       amdgpu_umc_fill_error_record(err_data, err_addr,
+                               retired_page, channel_index, umc_inst);
                }
        }
 

diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v8_10.c b/drivers/gpu/drm/amd/amdgpu/umc_v8_10.c
index a8cbda81828daf072943aa05315f6e5b48462bd8..38f9e29990cc431dfaa377536e2a1cc1b8a2eb25 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/umc_v8_10.c
+++ b/drivers/gpu/drm/amd/amdgpu/umc_v8_10.c
@@ -208,7 +208,10 @@ static void umc_v8_10_query_error_address(struct amdgpu_device *adev,
 {
        uint64_t mc_umc_status_addr;
        uint64_t mc_umc_status, err_addr;
-       uint32_t channel_index;
+       uint64_t mc_umc_addrt0, na_err_addr_base;
+       uint64_t na_err_addr, retired_page_addr;
+       uint32_t channel_index, addr_lsb, col = 0;
+       int ret = 0;
 
        mc_umc_status_addr =
                SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0);
@@ -229,13 +232,10 @@ static void umc_v8_10_query_error_address(struct amdgpu_device *adev,
                                        umc_inst * adev->umc.channel_inst_num +
                                        ch_inst];
 
-       /* calculate error address if ue/ce error is detected */
+       /* calculate error address if ue error is detected */
        if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
            REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, AddrV) == 1 &&
-           (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 ||
-            REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)) {
-               uint32_t addr_lsb;
-               uint64_t mc_umc_addrt0;
+           REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1) {
 
                mc_umc_addrt0 = SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_ADDRT0);
                err_addr = RREG64_PCIE((mc_umc_addrt0 + umc_reg_offset) * 4);
@@ -243,32 +243,24 @@ static void umc_v8_10_query_error_address(struct amdgpu_device *adev,
 
                /* the lowest lsb bits should be ignored */
                addr_lsb = REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, AddrLsb);
-
                err_addr &= ~((0x1ULL << addr_lsb) - 1);
-
-               /* we only save ue error information currently, ce is skipped */
-               if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1) {
-                       uint64_t na_err_addr_base = err_addr & ~(0x3ULL << UMC_V8_10_NA_C5_BIT);
-                       uint64_t na_err_addr, retired_page_addr;
-                       uint32_t col = 0;
-                       int ret = 0;
-
-                       /* loop for all possibilities of [C6 C5] in normal address. */
-                       for (col = 0; col < UMC_V8_10_NA_COL_2BITS_POWER_OF_2_NUM; col++) {
-                               na_err_addr = na_err_addr_base | (col << UMC_V8_10_NA_C5_BIT);
-
-                               /* Mapping normal error address to retired soc physical address. */
-                               ret = umc_v8_10_swizzle_mode_na_to_pa(adev, channel_index,
-                                                               na_err_addr, &retired_page_addr);
-                               if (ret) {
-                                       dev_err(adev->dev, "Failed to map pa from umc na.\n");
-                                       break;
-                               }
-                               dev_info(adev->dev, "Error Address(PA): 0x%llx\n",
-                                       retired_page_addr);
-                               amdgpu_umc_fill_error_record(err_data, na_err_addr,
-                                               retired_page_addr, channel_index, umc_inst);
+               na_err_addr_base = err_addr & ~(0x3ULL << UMC_V8_10_NA_C5_BIT);
+
+               /* loop for all possibilities of [C6 C5] in normal address. */
+               for (col = 0; col < UMC_V8_10_NA_COL_2BITS_POWER_OF_2_NUM; col++) {
+                       na_err_addr = na_err_addr_base | (col << UMC_V8_10_NA_C5_BIT);
+
+                       /* Mapping normal error address to retired soc physical address. */
+                       ret = umc_v8_10_swizzle_mode_na_to_pa(adev, channel_index,
+                                                       na_err_addr, &retired_page_addr);
+                       if (ret) {
+                               dev_err(adev->dev, "Failed to map pa from umc na.\n");
+                               break;
                        }
+                       dev_info(adev->dev, "Error Address(PA): 0x%llx\n",
+                               retired_page_addr);
+                       amdgpu_umc_fill_error_record(err_data, na_err_addr,
+                                       retired_page_addr, channel_index, umc_inst);
                }
        }
 

diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v8_7.c b/drivers/gpu/drm/amd/amdgpu/umc_v8_7.c
index f35253e0eaa6d62c7477b283eeb121c31b5b03e1..e2623685cb44f03a064ca08b43b459a1cdc1ffca 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/umc_v8_7.c
+++ b/drivers/gpu/drm/amd/amdgpu/umc_v8_7.c
@@ -130,10 +130,9 @@ static void umc_v8_7_ecc_info_query_error_address(struct amdgpu_device *adev,
        if (!err_data->err_addr)
                return;
 
-       /* calculate error address if ue/ce error is detected */
+       /* calculate error address if ue error is detected */
        if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
-           (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 ||
-           REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)) {
+           REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1) {
 
                err_addr = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_addr;
                err_addr = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr);
@@ -143,10 +142,7 @@ static void umc_v8_7_ecc_info_query_error_address(struct amdgpu_device *adev,
                                ADDR_OF_256B_BLOCK(channel_index) |
                                OFFSET_IN_256B_BLOCK(err_addr);
 
-               /* we only save ue error information currently, ce is skipped */
-               if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC)
-                               == 1)
-                       amdgpu_umc_fill_error_record(err_data, err_addr,
+               amdgpu_umc_fill_error_record(err_data, err_addr,
                                        retired_page, channel_index, umc_inst);
        }
 }
@@ -343,10 +339,9 @@ static void umc_v8_7_query_error_address(struct amdgpu_device *adev,
                return;
        }
 
-       /* calculate error address if ue/ce error is detected */
+       /* calculate error address if ue error is detected */
        if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
-           (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 ||
-           REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)) {
+           REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1) {
 
                err_addr = RREG64_PCIE((mc_umc_addrt0 + umc_reg_offset) * 4);
                /* the lowest lsb bits should be ignored */
@@ -359,10 +354,7 @@ static void umc_v8_7_query_error_address(struct amdgpu_device *adev,
                                ADDR_OF_256B_BLOCK(channel_index) |
                                OFFSET_IN_256B_BLOCK(err_addr);
 
-               /* we only save ue error information currently, ce is skipped */
-               if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC)
-                               == 1)
-                       amdgpu_umc_fill_error_record(err_data, err_addr,
+               amdgpu_umc_fill_error_record(err_data, err_addr,
                                        retired_page, channel_index, umc_inst);
        }