*
  * Write a start command to the ring.
  */
-static void vcn_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring)
+void vcn_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring)
 {
        struct amdgpu_device *adev = ring->adev;
 
  *
  * Write a end command to the ring.
  */
-static void vcn_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring)
+void vcn_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring)
 {
        struct amdgpu_device *adev = ring->adev;
 
  *
  * Write a nop command to the ring.
  */
-static void vcn_v2_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
+void vcn_v2_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 {
        struct amdgpu_device *adev = ring->adev;
        int i;
  *
  * Write a fence and a trap command to the ring.
  */
-static void vcn_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
-                                    unsigned flags)
+void vcn_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
+                               unsigned flags)
 {
        struct amdgpu_device *adev = ring->adev;
 
  *
  * Write ring commands to execute the indirect buffer
  */
-static void vcn_v2_0_dec_ring_emit_ib(struct amdgpu_ring *ring,
-                                     struct amdgpu_job *job,
-                                     struct amdgpu_ib *ib,
-                                     uint32_t flags)
+void vcn_v2_0_dec_ring_emit_ib(struct amdgpu_ring *ring,
+                              struct amdgpu_job *job,
+                              struct amdgpu_ib *ib,
+                              uint32_t flags)
 {
        struct amdgpu_device *adev = ring->adev;
        unsigned vmid = AMDGPU_JOB_GET_VMID(job);
        amdgpu_ring_write(ring, ib->length_dw);
 }
 
-static void vcn_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring,
-                                           uint32_t reg, uint32_t val,
-                                           uint32_t mask)
+void vcn_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
+                               uint32_t val, uint32_t mask)
 {
        struct amdgpu_device *adev = ring->adev;
 
        amdgpu_ring_write(ring, VCN_DEC_CMD_REG_READ_COND_WAIT << 1);
 }
 
-static void vcn_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
-                                           unsigned vmid, uint64_t pd_addr)
+void vcn_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
+                               unsigned vmid, uint64_t pd_addr)
 {
        struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
        uint32_t data0, data1, mask;
        vcn_v2_0_dec_ring_emit_reg_wait(ring, data0, data1, mask);
 }
 
-static void vcn_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring,
-                                       uint32_t reg, uint32_t val)
+void vcn_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring,
+                               uint32_t reg, uint32_t val)
 {
        struct amdgpu_device *adev = ring->adev;
 
  *
  * Write enc a fence and a trap command to the ring.
  */
-static void vcn_v2_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
-                       u64 seq, unsigned flags)
+void vcn_v2_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
+                               u64 seq, unsigned flags)
 {
        WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
 
        amdgpu_ring_write(ring, VCN_ENC_CMD_TRAP);
 }
 
-static void vcn_v2_0_enc_ring_insert_end(struct amdgpu_ring *ring)
+void vcn_v2_0_enc_ring_insert_end(struct amdgpu_ring *ring)
 {
        amdgpu_ring_write(ring, VCN_ENC_CMD_END);
 }
  *
  * Write enc ring commands to execute the indirect buffer
  */
-static void vcn_v2_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
-                                     struct amdgpu_job *job,
-                                     struct amdgpu_ib *ib,
-                                     uint32_t flags)
+void vcn_v2_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
+                              struct amdgpu_job *job,
+                              struct amdgpu_ib *ib,
+                              uint32_t flags)
 {
        unsigned vmid = AMDGPU_JOB_GET_VMID(job);
 
        amdgpu_ring_write(ring, ib->length_dw);
 }
 
-static void vcn_v2_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring,
-                                           uint32_t reg, uint32_t val,
-                                           uint32_t mask)
+void vcn_v2_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
+                               uint32_t val, uint32_t mask)
 {
        amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT);
        amdgpu_ring_write(ring, reg << 2);
        amdgpu_ring_write(ring, val);
 }
 
-static void vcn_v2_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
-                                           unsigned int vmid, uint64_t pd_addr)
+void vcn_v2_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
+                               unsigned int vmid, uint64_t pd_addr)
 {
        struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
 
                                        lower_32_bits(pd_addr), 0xffffffff);
 }
 
-static void vcn_v2_0_enc_ring_emit_wreg(struct amdgpu_ring *ring,
-                                       uint32_t reg, uint32_t val)
+void vcn_v2_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val)
 {
        amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE);
        amdgpu_ring_write(ring, reg << 2);
  *
  * Write a start command to the ring.
  */
-static void vcn_v2_0_jpeg_ring_insert_start(struct amdgpu_ring *ring)
+void vcn_v2_0_jpeg_ring_insert_start(struct amdgpu_ring *ring)
 {
        amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
                0, 0, PACKETJ_TYPE0));
  *
  * Write a end command to the ring.
  */
-static void vcn_v2_0_jpeg_ring_insert_end(struct amdgpu_ring *ring)
+void vcn_v2_0_jpeg_ring_insert_end(struct amdgpu_ring *ring)
 {
        amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
                0, 0, PACKETJ_TYPE0));
  *
  * Write a fence and a trap command to the ring.
  */
-static void vcn_v2_0_jpeg_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
-                                    unsigned flags)
+void vcn_v2_0_jpeg_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
+                               unsigned flags)
 {
        WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
 
  *
  * Write ring commands to execute the indirect buffer.
  */
-static void vcn_v2_0_jpeg_ring_emit_ib(struct amdgpu_ring *ring,
-                                      struct amdgpu_job *job,
-                                      struct amdgpu_ib *ib,
-                                      uint32_t flags)
+void vcn_v2_0_jpeg_ring_emit_ib(struct amdgpu_ring *ring,
+                               struct amdgpu_job *job,
+                               struct amdgpu_ib *ib,
+                               uint32_t flags)
 {
        unsigned vmid = AMDGPU_JOB_GET_VMID(job);
 
        amdgpu_ring_write(ring, 0x2);
 }
 
-static void vcn_v2_0_jpeg_ring_emit_reg_wait(struct amdgpu_ring *ring,
-                                           uint32_t reg, uint32_t val,
-                                           uint32_t mask)
+void vcn_v2_0_jpeg_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
+                               uint32_t val, uint32_t mask)
 {
        uint32_t reg_offset = (reg << 2);
 
        amdgpu_ring_write(ring, mask);
 }
 
-static void vcn_v2_0_jpeg_ring_emit_vm_flush(struct amdgpu_ring *ring,
-               unsigned vmid, uint64_t pd_addr)
+void vcn_v2_0_jpeg_ring_emit_vm_flush(struct amdgpu_ring *ring,
+                               unsigned vmid, uint64_t pd_addr)
 {
        struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
        uint32_t data0, data1, mask;
        vcn_v2_0_jpeg_ring_emit_reg_wait(ring, data0, data1, mask);
 }
 
-static void vcn_v2_0_jpeg_ring_emit_wreg(struct amdgpu_ring *ring,
-                                       uint32_t reg, uint32_t val)
+void vcn_v2_0_jpeg_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val)
 {
        uint32_t reg_offset = (reg << 2);
 
        amdgpu_ring_write(ring, val);
 }
 
-static void vcn_v2_0_jpeg_ring_nop(struct amdgpu_ring *ring, uint32_t count)
+void vcn_v2_0_jpeg_ring_nop(struct amdgpu_ring *ring, uint32_t count)
 {
        int i;
 
 
 #ifndef __VCN_V2_0_H__
 #define __VCN_V2_0_H__
 
+extern void vcn_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring);
+extern void vcn_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring);
+extern void vcn_v2_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
+extern void vcn_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
+                               unsigned flags);
+extern void vcn_v2_0_dec_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_job *job,
+                               struct amdgpu_ib *ib, uint32_t flags);
+extern void vcn_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
+                               uint32_t val, uint32_t mask);
+extern void vcn_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
+                               unsigned vmid, uint64_t pd_addr);
+extern void vcn_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring,
+                               uint32_t reg, uint32_t val);
+
+extern void vcn_v2_0_enc_ring_insert_end(struct amdgpu_ring *ring);
+extern void vcn_v2_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
+                               u64 seq, unsigned flags);
+extern void vcn_v2_0_enc_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_job *job,
+                               struct amdgpu_ib *ib, uint32_t flags);
+extern void vcn_v2_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
+                               uint32_t val, uint32_t mask);
+extern void vcn_v2_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
+                               unsigned int vmid, uint64_t pd_addr);
+extern void vcn_v2_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
+
+extern void vcn_v2_0_jpeg_ring_insert_start(struct amdgpu_ring *ring);
+extern void vcn_v2_0_jpeg_ring_insert_end(struct amdgpu_ring *ring);
+extern void vcn_v2_0_jpeg_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
+                               unsigned flags);
+extern void vcn_v2_0_jpeg_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_job *job,
+                               struct amdgpu_ib *ib, uint32_t flags);
+extern void vcn_v2_0_jpeg_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
+                               uint32_t val, uint32_t mask);
+extern void vcn_v2_0_jpeg_ring_emit_vm_flush(struct amdgpu_ring *ring,
+                               unsigned vmid, uint64_t pd_addr);
+extern void vcn_v2_0_jpeg_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
+extern void vcn_v2_0_jpeg_ring_nop(struct amdgpu_ring *ring, uint32_t count);
+
 extern const struct amdgpu_ip_block_version vcn_v2_0_ip_block;
 
 #endif /* __VCN_V2_0_H__ */