PCI: Disable D3cold on Asus B1400 PCI-NVMe bridge

The Asus B1400 with original shipped firmware versions and VMD disabled
cannot resume from suspend: the NVMe device becomes unresponsive and
inaccessible.

This appears to be an untested D3cold transition by the vendor; Intel
socwatch shows that Windows leaves the NVMe device and parent bridge in D0
during suspend, even though these firmware versions have StorageD3Enable=1.

The NVMe device and parent PCI bridge both share the same "PXP" ACPI power
resource, which gets turned off as both devices are put into D3cold during
suspend. The _OFF() method calls DL23() which sets a L23E bit at offset
0xe2 into the PCI configuration space for this root port.  This is the
specific write that the _ON() routine is unable to recover from. This
register is not documented in the public chipset datasheet.

Disallow D3cold on the PCI bridge to enable successful suspend/resume.

Link: https://bugzilla.kernel.org/show_bug.cgi?id=215742
Link: https://lore.kernel.org/r/20240228075316.7404-1-drake@endlessos.org
Signed-off-by: Daniel Drake <drake@endlessos.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Jian-Hong Pan <jhp@endlessos.org>
Acked-by: Rafael J. Wysocki <rafael@kernel.org>

diff --git a/arch/x86/pci/fixup.c b/arch/x86/pci/fixup.c
index f347c20247d307752ab8260b94654aa988816de1..b33afb240601b006d5fd27b5245fed16354f3f71 100644 (file)
--- a/arch/x86/pci/fixup.c
+++ b/arch/x86/pci/fixup.c
@@ -907,6 +907,54 @@ static void chromeos_fixup_apl_pci_l1ss_capability(struct pci_dev *dev)
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x5ad6, chromeos_save_apl_pci_l1ss_capability);
 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x5ad6, chromeos_fixup_apl_pci_l1ss_capability);
 
+/*
+ * Disable D3cold on Asus B1400 PCI-NVMe bridge
+ *
+ * On this platform with VMD off, the NVMe device cannot successfully power
+ * back on from D3cold. This appears to be an untested transition by the
+ * vendor: Windows leaves the NVMe and parent bridge in D0 during suspend.
+ *
+ * We disable D3cold on the parent bridge for simplicity, and the fact that
+ * both parent bridge and NVMe device share the same power resource.
+ *
+ * This is only needed on BIOS versions before 308; the newer versions flip
+ * StorageD3Enable from 1 to 0.
+ */
+static const struct dmi_system_id asus_nvme_broken_d3cold_table[] = {
+       {
+               .matches = {
+                               DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
+                               DMI_MATCH(DMI_BIOS_VERSION, "B1400CEAE.304"),
+               },
+       },
+       {
+               .matches = {
+                               DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
+                               DMI_MATCH(DMI_BIOS_VERSION, "B1400CEAE.305"),
+               },
+       },
+       {
+               .matches = {
+                               DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
+                               DMI_MATCH(DMI_BIOS_VERSION, "B1400CEAE.306"),
+               },
+       },
+       {
+               .matches = {
+                               DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
+                               DMI_MATCH(DMI_BIOS_VERSION, "B1400CEAE.307"),
+               },
+       },
+       {}
+};
+
+static void asus_disable_nvme_d3cold(struct pci_dev *pdev)
+{
+       if (dmi_check_system(asus_nvme_broken_d3cold_table) > 0)
+               pci_d3cold_disable(pdev);
+}
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x9a09, asus_disable_nvme_d3cold);
+
 #ifdef CONFIG_SUSPEND
 /*
  * Root Ports on some AMD SoCs advertise PME_Support for D3hot and D3cold, but