drm/amdgpu: optimize amdgpu_device_vram_access a bit.

Only write the _HI register when necessary.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Acked-by: Jonathan Kim <Jonathan.Kim@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index a86e80842df9ba72bfbbbed0fc7762af45e4939b..5d24b1436b9f9f2672a8c347253d81f27d61864c 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -183,20 +183,25 @@ bool amdgpu_device_supports_baco(struct drm_device *dev)
 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
                               uint32_t *buf, size_t size, bool write)
 {
-       uint64_t last;
        unsigned long flags;
+       uint32_t hi = ~0;
+       uint64_t last;
+
+       spin_lock_irqsave(&adev->mmio_idx_lock, flags);
+       for (last = pos + size; pos < last; pos += 4) {
+               uint32_t tmp = pos >> 31;
 
-       last = size - 4;
-       for (last += pos; pos <= last; pos += 4) {
-               spin_lock_irqsave(&adev->mmio_idx_lock, flags);
                WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)pos) | 0x80000000);
-               WREG32_NO_KIQ(mmMM_INDEX_HI, pos >> 31);
+               if (tmp != hi) {
+                       WREG32_NO_KIQ(mmMM_INDEX_HI, tmp);
+                       hi = tmp;
+               }
                if (write)
                        WREG32_NO_KIQ(mmMM_DATA, *buf++);
                else
                        *buf++ = RREG32_NO_KIQ(mmMM_DATA);
-               spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
        }
+       spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
 }
 
 /*