drm/amd/display: Add missing dwb registers

DCN3.0 supports some specific DWB debug registers that are not exposed
yet. This commit just adds the missing registers.

Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb.h
index 332634b76aacdad95c3fdcf7865bc3a8f67c08c6..0f3f7c5fbaecf95222a3d3da64404e7867b7826d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb.h
@@ -217,6 +217,7 @@
        SF_DWB2(DWB_OGAM_LUT_DATA, DWBCP, 0, DWB_OGAM_LUT_DATA, mask_sh),\
        SF_DWB2(DWB_OGAM_LUT_CONTROL, DWBCP, 0, DWB_OGAM_LUT_WRITE_COLOR_MASK, mask_sh),\
        SF_DWB2(DWB_OGAM_LUT_CONTROL, DWBCP, 0, DWB_OGAM_LUT_READ_COLOR_SEL, mask_sh),\
+       SF_DWB2(DWB_OGAM_LUT_CONTROL, DWBCP, 0, DWB_OGAM_LUT_READ_DBG, mask_sh),\
        SF_DWB2(DWB_OGAM_LUT_CONTROL, DWBCP, 0, DWB_OGAM_LUT_HOST_SEL, mask_sh),\
        SF_DWB2(DWB_OGAM_LUT_CONTROL, DWBCP, 0, DWB_OGAM_LUT_CONFIG_MODE, mask_sh),\
        SF_DWB2(DWB_OGAM_RAMA_START_CNTL_B, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION_START_B, mask_sh),\
@@ -524,6 +525,7 @@
        type DWB_OGAM_LUT_DATA;\
        type DWB_OGAM_LUT_WRITE_COLOR_MASK;\
        type DWB_OGAM_LUT_READ_COLOR_SEL;\
+       type DWB_OGAM_LUT_READ_DBG;\
        type DWB_OGAM_LUT_HOST_SEL;\
        type DWB_OGAM_LUT_CONFIG_MODE;\
        type DWB_OGAM_LUT_STATUS;\
@@ -710,7 +712,7 @@
        type DWB_OGAM_RAMB_EXP_REGION32_LUT_OFFSET;\
        type DWB_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS;\
        type DWB_OGAM_RAMB_EXP_REGION33_LUT_OFFSET;\
-       type DWB_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS;
+       type DWB_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS
 
 struct dcn30_dwbc_registers {
        /* DCN3AG */
@@ -733,6 +735,10 @@ struct dcn30_dwbc_registers {
        uint32_t DWB_MMHUBBUB_BACKPRESSURE_CNT;
        uint32_t DWB_HOST_READ_CONTROL;
        uint32_t DWB_SOFT_RESET;
+       uint32_t DWB_DEBUG_CTRL;
+       uint32_t DWB_DEBUG;
+       uint32_t DWB_TEST_DEBUG_INDEX;
+       uint32_t DWB_TEST_DEBUG_DATA;
 
        /* DWBSCL */
        uint32_t DWBSCL_COEF_RAM_TAP_SELECT;
@@ -747,6 +753,9 @@ struct dcn30_dwbc_registers {
        uint32_t DWBSCL_DEST_SIZE;
        uint32_t DWBSCL_OVERFLOW_STATUS;
        uint32_t DWBSCL_OVERFLOW_COUNTER;
+       uint32_t DWBSCL_DEBUG;
+       uint32_t DWBSCL_TEST_DEBUG_INDEX;
+       uint32_t DWBSCL_TEST_DEBUG_DATA;
 
        /* DWBCP */
        uint32_t DWB_HDR_MULT_COEF;
@@ -838,6 +847,9 @@ struct dcn30_dwbc_registers {
        uint32_t DWB_OGAM_RAMB_REGION_28_29;
        uint32_t DWB_OGAM_RAMB_REGION_30_31;
        uint32_t DWB_OGAM_RAMB_REGION_32_33;
+       uint32_t DWBCP_DEBUG;
+       uint32_t DWBCP_TEST_DEBUG_INDEX;
+       uint32_t DWBCP_TEST_DEBUG_DATA;
 };
 
 /* Internal enums / structs */