arm64: dts: mediatek: mt8183: Fix systimer 13 MHz clock description
authorChen-Yu Tsai <wenst@chromium.org>
Thu, 1 Dec 2022 08:42:26 +0000 (16:42 +0800)
committerMatthias Brugger <matthias.bgg@gmail.com>
Mon, 9 Jan 2023 16:16:48 +0000 (17:16 +0100)
The systimer block derives its 13 MHz clock by dividing the main 26 MHz
oscillator clock by 2 internally, not through the TOPCKGEN clock
controller.

On the MT8183 this divider is set either by power-on-reset or by the
bootloader. The bootloader may then make the divider unconfigurable to,
but can be read out by, the operating system.

Making the systimer block take the 26 MHz clock directly requires
changing the implementations. As an ABI compatible fix, change the
input clock of the systimer block a fixed factor divide-by-2 clock
that takes the 26 MHz oscillator as its input.

Fixes: 5bc8e2875ffb ("arm64: dts: mt8183: add systimer0 device node")
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20221201084229.3464449-2-wenst@chromium.org
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
arch/arm64/boot/dts/mediatek/mt8183.dtsi

index 402136bfd5350b044d7fb74c6338c3273c14e0f5..268a1f28af8cea1d82b657f33d348db0781b53eb 100644 (file)
                method = "smc";
        };
 
+       clk13m: fixed-factor-clock-13m {
+               compatible = "fixed-factor-clock";
+               #clock-cells = <0>;
+               clocks = <&clk26m>;
+               clock-div = <2>;
+               clock-mult = <1>;
+               clock-output-names = "clk13m";
+       };
+
        clk26m: oscillator {
                compatible = "fixed-clock";
                #clock-cells = <0>;
                                     "mediatek,mt6765-timer";
                        reg = <0 0x10017000 0 0x1000>;
                        interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&topckgen CLK_TOP_CLK13M>;
-                       clock-names = "clk13m";
+                       clocks = <&clk13m>;
                };
 
                iommu: iommu@10205000 {