ARM: dts: qcom: sdx65: Add support for APCS block

The APCS block on SDX65 acts as a mailbox controller and also provides
clock output for the Cortex A7 CPU.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1645505785-2271-5-git-send-email-quic_rohiagar@quicinc.com

diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi
index 6b3a502c0ce28f20f6cb08958e69a1644a5bbec0..14579121be5a48a145bc42dcdb142ebae8e98918 100644 (file)
--- a/arch/arm/boot/dts/qcom-sdx65.dtsi
+++ b/arch/arm/boot/dts/qcom-sdx65.dtsi
@@ -129,6 +129,15 @@
                        #clock-cells = <0>;
                };
 
+               apcs: mailbox@17810000 {
+                       compatible = "qcom,sdx55-apcs-gcc", "syscon";
+                       reg = <0x17810000 0x2000>;
+                       #mbox-cells = <1>;
+                       clocks = <&rpmhcc RPMH_CXO_CLK>, <&a7pll>, <&gcc GPLL0>;
+                       clock-names = "ref", "pll", "aux";
+                       #clock-cells = <0>;
+               };
+
                timer@17820000 {
                        #address-cells = <1>;
                        #size-cells = <1>;