clk: renesas: r8a779g0: Add SCIF clocks
authorGeert Uytterhoeven <geert+renesas@glider.be>
Fri, 7 Oct 2022 13:10:02 +0000 (15:10 +0200)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Wed, 26 Oct 2022 10:38:01 +0000 (12:38 +0200)
Add the module clocks used by the Serial Communication Interfaces with
FIFO (SCIF) on the Renesas R-Car V4H (R8A779G0) SoC.

Based on a larger patch in the BSP by Kazuya Mizuguchi.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/a6ab466cfdac377106494c00b811a60151cb1825.1665147497.git.geert+renesas@glider.be
drivers/clk/renesas/r8a779g0-cpg-mssr.c

index f1f0496f7605f554936ad37c3b755f31fb785392..c8c143c31b2beac0e45671279d94d4fed4bf706a 100644 (file)
@@ -175,6 +175,10 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
        DEF_MOD("msi3",         621,    R8A779G0_CLK_MSO),
        DEF_MOD("msi4",         622,    R8A779G0_CLK_MSO),
        DEF_MOD("msi5",         623,    R8A779G0_CLK_MSO),
+       DEF_MOD("scif0",        702,    R8A779G0_CLK_SASYNCPERD4),
+       DEF_MOD("scif1",        703,    R8A779G0_CLK_SASYNCPERD4),
+       DEF_MOD("scif3",        704,    R8A779G0_CLK_SASYNCPERD4),
+       DEF_MOD("scif4",        705,    R8A779G0_CLK_SASYNCPERD4),
        DEF_MOD("sydm0",        709,    R8A779G0_CLK_S0D6_PER),
        DEF_MOD("sydm1",        710,    R8A779G0_CLK_S0D6_PER),
        DEF_MOD("wdt1:wdt0",    907,    R8A779G0_CLK_R),