drm/amd/display: Add new Replay command and Disabled Replay Timing Resync

[why]
To support dynamic switching for Replay timing sync mechanism.

Reviewed-by: ChunTao Tso <chuntao.tso@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Dennis Chan <dennis.chan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
index fcb825e4f1bb8f8dfba4107bc3bb9c642aa726f1..edf60c4f318cc18fd5c6fcc1c25c810fa200e4f1 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -1022,6 +1022,16 @@ enum replay_coasting_vtotal_type {
        PR_COASTING_TYPE_NUM,
 };
 
+/*
+ * This is general Interface for Replay to
+ * set an 32 bit variable to dmub
+ * The Message_type indicates which variable
+ * passed to DMUB.
+ */
+enum replay_FW_Message_type {
+       Replay_Set_Timing_Sync_Supported,
+};
+
 union replay_error_status {
        struct {
                unsigned char STATE_TRANSITION_ERROR    :1;

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.h b/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.h
index e8385bbf51fc2a4ab2730af4274078780b7189cd..427bc47a676e6c44f6cb329634810bd40a419b59 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.h
@@ -45,6 +45,9 @@ struct dmub_replay_funcs {
                struct replay_context *replay_context, uint8_t panel_inst);
        void (*replay_set_power_opt)(struct dmub_replay *dmub, unsigned int power_opt,
                uint8_t panel_inst);
+       void (*replay_send_cmd)(struct dmub_replay *dmub,
+               enum replay_FW_Message_type msg, unsigned int panel_inst,
+               uint32_t cmd_data);
        void (*replay_set_coasting_vtotal)(struct dmub_replay *dmub, uint16_t coasting_vtotal,
                uint8_t panel_inst);
        void (*replay_residency)(struct dmub_replay *dmub,

diff --git a/drivers/gpu/drm/amd/display/dc/inc/link.h b/drivers/gpu/drm/amd/display/dc/inc/link.h
index d7685368140ab5856fde83566a412b4a3a24e936..dd3f53151d8b8cc589853853900d1cdacb106045 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/link.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/link.h
@@ -281,6 +281,9 @@ struct link_service {
                        const unsigned int *power_opts);
        bool (*edp_setup_replay)(struct dc_link *link,
                        const struct dc_stream_state *stream);
+       bool (*edp_send_replay_cmd)(struct dc_link *link,
+                       enum replay_FW_Message_type msg,
+                       uint32_t params);
        bool (*edp_set_coasting_vtotal)(
                        struct dc_link *link, uint16_t coasting_vtotal);
        bool (*edp_replay_residency)(const struct dc_link *link,

diff --git a/drivers/gpu/drm/amd/display/dc/link/link_factory.c b/drivers/gpu/drm/amd/display/dc/link/link_factory.c
index 7abfc67d10a62da2171aa14dc26c6075fde74409..6b306ea58b9bcedd1211a4d34a3913cda6d3da32 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/link/link_factory.c
+++ b/drivers/gpu/drm/amd/display/dc/link/link_factory.c
@@ -213,6 +213,7 @@ static void construct_link_service_edp_panel_control(struct link_service *link_s
        link_srv->edp_get_replay_state = edp_get_replay_state;
        link_srv->edp_set_replay_allow_active = edp_set_replay_allow_active;
        link_srv->edp_setup_replay = edp_setup_replay;
+       link_srv->edp_send_replay_cmd = edp_send_replay_cmd;
        link_srv->edp_set_coasting_vtotal = edp_set_coasting_vtotal;
        link_srv->edp_replay_residency = edp_replay_residency;
 

diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
index e32a7974a4bc68c1dcf5767d805a6c66ecf97772..c52b51b2b4b389c3123213b01443a2bd27519dcf 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
@@ -1007,6 +1007,30 @@ bool edp_setup_replay(struct dc_link *link, const struct dc_stream_state *stream
        return true;
 }
 
+/*
+ * This is general Interface for Replay to set an 32 bit variable to dmub
+ * replay_FW_Message_type: Indicates which instruction or variable pass to DMUB
+ * cmd_data: Value of the config.
+ */
+bool edp_send_replay_cmd(struct dc_link *link,
+                       enum replay_FW_Message_type msg,
+                       uint32_t cmd_data)
+{
+       struct dc *dc = link->ctx->dc;
+       struct dmub_replay *replay = dc->res_pool->replay;
+       unsigned int panel_inst;
+
+       if (!replay)
+               return false;
+
+       if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
+               return false;
+
+       replay->funcs->replay_send_cmd(replay, msg, cmd_data, panel_inst);
+
+       return true;
+}
+
 bool edp_set_coasting_vtotal(struct dc_link *link, uint16_t coasting_vtotal)
 {
        struct dc *dc = link->ctx->dc;

diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.h b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.h
index ebf7deb63d136e95b5da85ac0bb4a01675940a5f..6b223580ac8a79245db95cbaf1cd433438bbc1fa 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.h
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.h
@@ -57,6 +57,9 @@ bool edp_set_replay_allow_active(struct dc_link *dc_link, const bool *enable,
        bool wait, bool force_static, const unsigned int *power_opts);
 bool edp_setup_replay(struct dc_link *link,
                const struct dc_stream_state *stream);
+bool edp_send_replay_cmd(struct dc_link *link,
+                       enum replay_FW_Message_type msg,
+                       uint32_t params);
 bool edp_set_coasting_vtotal(struct dc_link *link, uint16_t coasting_vtotal);
 bool edp_replay_residency(const struct dc_link *link,
        unsigned int *residency, const bool is_start, const bool is_alpm);