arm64: dts: renesas: r9a08g045: Add watchdog node

Add the DT node for the watchdog IP accessible by Cortex-A of RZ/G3S
SoC (R9108G045).

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20240122111115.2861835-10-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
index 5facfad9615838ecf422adc71905b40d033e08b1..dfee878c0f4922584921fa2c60e8995529339b24 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
@@ -264,6 +264,20 @@
                              <0x0 0x12440000 0 0x60000>;
                        interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
                };
+
+               wdt0: watchdog@12800800 {
+                       compatible = "renesas,r9a08g045-wdt", "renesas,rzg2l-wdt";
+                       reg = <0 0x12800800 0 0x400>;
+                       clocks = <&cpg CPG_MOD R9A08G045_WDT0_PCLK>,
+                                <&cpg CPG_MOD R9A08G045_WDT0_CLK>;
+                       clock-names = "pclk", "oscclk";
+                       interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "wdt", "perrout";
+                       resets = <&cpg R9A08G045_WDT0_PRESETN>;
+                       power-domains = <&cpg>;
+                       status = "disabled";
+               };
        };
 
        timer {