drm/msm/a6xx: Add missing BIT(7) to REG_A6XX_UCHE_CLIENT_PF

Downstream always set BIT(7)

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Patchwork: https://patchwork.freedesktop.org/patch/568930/

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 7a0220d29a235b34334092fc6a1d12a6f2e1312b..e5558d5e0aa24e4f7d5e89382a6a8e654dc53d93 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -1782,7 +1782,7 @@ static int hw_init(struct msm_gpu *gpu)
        else
                gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x1fffff);
 
-       gpu_write(gpu, REG_A6XX_UCHE_CLIENT_PF, 1);
+       gpu_write(gpu, REG_A6XX_UCHE_CLIENT_PF, BIT(7) | 0x1);
 
        /* Set weights for bicubic filtering */
        if (adreno_is_a650_family(adreno_gpu)) {