accel/habanalabs/gaudi2 : remove psoc_arc access

Because firmware is blocking PSOC_ARC_DBG, we need to disable access
to this block.

Signed-off-by: Benjamin Dotan <bdotan@habana.ai>
Reviewed-by: Oded Gabbay <ogabbay@kernel.org>
Signed-off-by: Oded Gabbay <ogabbay@kernel.org>

diff --git a/drivers/accel/habanalabs/gaudi2/gaudi2_coresight.c b/drivers/accel/habanalabs/gaudi2/gaudi2_coresight.c
index 25b5368f37dde96d005ac45db4a573b90729ff85..3e90bc9692646a3b71f2be9732873d107d20bbe1 100644 (file)
--- a/drivers/accel/habanalabs/gaudi2/gaudi2_coresight.c
+++ b/drivers/accel/habanalabs/gaudi2/gaudi2_coresight.c
@@ -151,8 +151,8 @@ static u64 debug_stm_regs[GAUDI2_STM_LAST + 1] = {
        [GAUDI2_STM_DCORE3_VDEC1_CS] = mmDCORE3_VDEC1_CS_STM_BASE,
        [GAUDI2_STM_PCIE] = mmPCIE_STM_BASE,
        [GAUDI2_STM_PSOC] = mmPSOC_STM_BASE,
-       [GAUDI2_STM_PSOC_ARC0_CS] = mmPSOC_ARC0_CS_STM_BASE,
-       [GAUDI2_STM_PSOC_ARC1_CS] = mmPSOC_ARC1_CS_STM_BASE,
+       [GAUDI2_STM_PSOC_ARC0_CS] = 0,
+       [GAUDI2_STM_PSOC_ARC1_CS] = 0,
        [GAUDI2_STM_PDMA0_CS] = mmPDMA0_CS_STM_BASE,
        [GAUDI2_STM_PDMA1_CS] = mmPDMA1_CS_STM_BASE,
        [GAUDI2_STM_CPU] = mmCPU_STM_BASE,
@@ -293,8 +293,8 @@ static u64 debug_etf_regs[GAUDI2_ETF_LAST + 1] = {
        [GAUDI2_ETF_DCORE3_VDEC1_CS] = mmDCORE3_VDEC1_CS_ETF_BASE,
        [GAUDI2_ETF_PCIE] = mmPCIE_ETF_BASE,
        [GAUDI2_ETF_PSOC] = mmPSOC_ETF_BASE,
-       [GAUDI2_ETF_PSOC_ARC0_CS] = mmPSOC_ARC0_CS_ETF_BASE,
-       [GAUDI2_ETF_PSOC_ARC1_CS] = mmPSOC_ARC1_CS_ETF_BASE,
+       [GAUDI2_ETF_PSOC_ARC0_CS] = 0,
+       [GAUDI2_ETF_PSOC_ARC1_CS] = 0,
        [GAUDI2_ETF_PDMA0_CS] = mmPDMA0_CS_ETF_BASE,
        [GAUDI2_ETF_PDMA1_CS] = mmPDMA1_CS_ETF_BASE,
        [GAUDI2_ETF_CPU_0] = mmCPU_ETF_0_BASE,
@@ -436,8 +436,8 @@ static u64 debug_funnel_regs[GAUDI2_FUNNEL_LAST + 1] = {
        [GAUDI2_FUNNEL_DCORE3_RTR6] = mmDCORE3_RTR6_FUNNEL_BASE,
        [GAUDI2_FUNNEL_DCORE3_RTR7] = mmDCORE3_RTR7_FUNNEL_BASE,
        [GAUDI2_FUNNEL_PSOC] = mmPSOC_FUNNEL_BASE,
-       [GAUDI2_FUNNEL_PSOC_ARC0] = mmPSOC_ARC0_FUNNEL_BASE,
-       [GAUDI2_FUNNEL_PSOC_ARC1] = mmPSOC_ARC1_FUNNEL_BASE,
+       [GAUDI2_FUNNEL_PSOC_ARC0] = 0,
+       [GAUDI2_FUNNEL_PSOC_ARC1] = 0,
        [GAUDI2_FUNNEL_XDMA] = mmXDMA_FUNNEL_BASE,
        [GAUDI2_FUNNEL_CPU] = mmCPU_FUNNEL_BASE,
        [GAUDI2_FUNNEL_PMMU] = mmPMMU_FUNNEL_BASE,
@@ -766,10 +766,10 @@ static u64 debug_bmon_regs[GAUDI2_BMON_LAST + 1] = {
        [GAUDI2_BMON_PCIE_MSTR_RD] = mmPCIE_BMON_MSTR_RD_BASE,
        [GAUDI2_BMON_PCIE_SLV_WR] = mmPCIE_BMON_SLV_WR_BASE,
        [GAUDI2_BMON_PCIE_SLV_RD] = mmPCIE_BMON_SLV_RD_BASE,
-       [GAUDI2_BMON_PSOC_ARC0_0] = mmPSOC_ARC0_BMON_0_BASE,
-       [GAUDI2_BMON_PSOC_ARC0_1] = mmPSOC_ARC0_BMON_1_BASE,
-       [GAUDI2_BMON_PSOC_ARC1_0] = mmPSOC_ARC1_BMON_0_BASE,
-       [GAUDI2_BMON_PSOC_ARC1_1] = mmPSOC_ARC1_BMON_1_BASE,
+       [GAUDI2_BMON_PSOC_ARC0_0] = 0,
+       [GAUDI2_BMON_PSOC_ARC0_1] = 0,
+       [GAUDI2_BMON_PSOC_ARC1_0] = 0,
+       [GAUDI2_BMON_PSOC_ARC1_1] = 0,
        [GAUDI2_BMON_PDMA0_0] = mmPDMA0_BMON_0_BASE,
        [GAUDI2_BMON_PDMA0_1] = mmPDMA0_BMON_1_BASE,
        [GAUDI2_BMON_PDMA1_0] = mmPDMA1_BMON_0_BASE,
@@ -968,8 +968,8 @@ static u64 debug_spmu_regs[GAUDI2_SPMU_LAST + 1] = {
        [GAUDI2_SPMU_DCORE3_VDEC0_CS] = mmDCORE3_VDEC0_CS_SPMU_BASE,
        [GAUDI2_SPMU_DCORE3_VDEC1_CS] = mmDCORE3_VDEC1_CS_SPMU_BASE,
        [GAUDI2_SPMU_PCIE] = mmPCIE_SPMU_BASE,
-       [GAUDI2_SPMU_PSOC_ARC0_CS] = mmPSOC_ARC0_CS_SPMU_BASE,
-       [GAUDI2_SPMU_PSOC_ARC1_CS] = mmPSOC_ARC1_CS_SPMU_BASE,
+       [GAUDI2_SPMU_PSOC_ARC0_CS] = 0,
+       [GAUDI2_SPMU_PSOC_ARC1_CS] = 0,
        [GAUDI2_SPMU_PDMA0_CS] = mmPDMA0_CS_SPMU_BASE,
        [GAUDI2_SPMU_PDMA1_CS] = mmPDMA1_CS_SPMU_BASE,
        [GAUDI2_SPMU_PMMU_CS] = mmPMMU_CS_SPMU_BASE,