powerpc/xive: Remove P9 DD1 flag XIVE_IRQ_FLAG_EOI_FW

This flag was used to support the P9 DD1 and we have stopped
supporting this CPU when DD2 came out. See skiboot commit:

  https://github.com/open-power/skiboot/commit/0b0d15e3c170

Also, remove eoi handler which is now unused.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20201210171450.1933725-11-clg@kaod.org

diff --git a/arch/powerpc/include/asm/opal-api.h b/arch/powerpc/include/asm/opal-api.h
index 0455b679c050413ea1c56e801aad734f896cde6b..0b63ba7d59175f3d00d6d5a03853c0851279abb4 100644 (file)
--- a/arch/powerpc/include/asm/opal-api.h
+++ b/arch/powerpc/include/asm/opal-api.h
@@ -1093,7 +1093,7 @@ enum {
        OPAL_XIVE_IRQ_LSI               = 0x00000004,
        OPAL_XIVE_IRQ_SHIFT_BUG         = 0x00000008, /* P9 DD1.0 workaround */
        OPAL_XIVE_IRQ_MASK_VIA_FW       = 0x00000010, /* P9 DD1.0 workaround */
-       OPAL_XIVE_IRQ_EOI_VIA_FW        = 0x00000020,
+       OPAL_XIVE_IRQ_EOI_VIA_FW        = 0x00000020, /* P9 DD1.0 workaround */
 };
 
 /* Flags for OPAL_XIVE_GET/SET_QUEUE_INFO */

diff --git a/arch/powerpc/include/asm/xive.h b/arch/powerpc/include/asm/xive.h
index 8d5b0dcc253c05abef041ac1f4a8c13184c056d0..9a312b975ca826e2782b2eb3b3b89dcd0412b67d 100644 (file)
--- a/arch/powerpc/include/asm/xive.h
+++ b/arch/powerpc/include/asm/xive.h
@@ -62,7 +62,7 @@ struct xive_irq_data {
 #define XIVE_IRQ_FLAG_LSI      0x02
 /* #define XIVE_IRQ_FLAG_SHIFT_BUG     0x04 */ /* P9 DD1.0 workaround */
 /* #define XIVE_IRQ_FLAG_MASK_FW       0x08 */ /* P9 DD1.0 workaround */
-#define XIVE_IRQ_FLAG_EOI_FW   0x10
+/* #define XIVE_IRQ_FLAG_EOI_FW        0x10 */ /* P9 DD1.0 workaround */
 #define XIVE_IRQ_FLAG_H_INT_ESB        0x20
 
 /* Special flag set by KVM for excalation interrupts */

diff --git a/arch/powerpc/kvm/book3s_xive_template.c b/arch/powerpc/kvm/book3s_xive_template.c
index ece36e024a8f89c386320ac02f7bfadf15be8ec6..b0015e05d99a94478d5269313dfe0a249ac23d3c 100644 (file)
--- a/arch/powerpc/kvm/book3s_xive_template.c
+++ b/arch/powerpc/kvm/book3s_xive_template.c
@@ -74,8 +74,6 @@ static void GLUE(X_PFX,source_eoi)(u32 hw_irq, struct xive_irq_data *xd)
        /* If the XIVE supports the new "store EOI facility, use it */
        if (xd->flags & XIVE_IRQ_FLAG_STORE_EOI)
                __x_writeq(0, __x_eoi_page(xd) + XIVE_ESB_STORE_EOI);
-       else if (hw_irq && xd->flags & XIVE_IRQ_FLAG_EOI_FW)
-               opal_int_eoi(hw_irq);
        else if (xd->flags & XIVE_IRQ_FLAG_LSI) {
                /*
                 * For LSIs the HW EOI cycle is used rather than PQ bits,

diff --git a/arch/powerpc/sysdev/xive/common.c b/arch/powerpc/sysdev/xive/common.c
index 9165d4834b2d1a6117360ca31358280724892a1e..3e91ec4bb49e34926cf88723a327540d449cac42 100644 (file)
--- a/arch/powerpc/sysdev/xive/common.c
+++ b/arch/powerpc/sysdev/xive/common.c
@@ -354,18 +354,7 @@ static void xive_do_source_eoi(u32 hw_irq, struct xive_irq_data *xd)
        /* If the XIVE supports the new "store EOI facility, use it */
        if (xd->flags & XIVE_IRQ_FLAG_STORE_EOI)
                xive_esb_write(xd, XIVE_ESB_STORE_EOI, 0);
-       else if (hw_irq && xd->flags & XIVE_IRQ_FLAG_EOI_FW) {
-               /*
-                * The FW told us to call it. This happens for some
-                * interrupt sources that need additional HW whacking
-                * beyond the ESB manipulation. For example LPC interrupts
-                * on P9 DD1.0 needed a latch to be clared in the LPC bridge
-                * itself. The Firmware will take care of it.
-                */
-               if (WARN_ON_ONCE(!xive_ops->eoi))
-                       return;
-               xive_ops->eoi(hw_irq);
-       } else {
+       else {
                u8 eoi_val;
 
                /*
@@ -1267,7 +1256,6 @@ static const struct {
 } xive_irq_flags[] = {
        { XIVE_IRQ_FLAG_STORE_EOI, "STORE_EOI" },
        { XIVE_IRQ_FLAG_LSI,       "LSI"       },
-       { XIVE_IRQ_FLAG_EOI_FW,    "EOI_FW"    },
        { XIVE_IRQ_FLAG_H_INT_ESB, "H_INT_ESB" },
        { XIVE_IRQ_FLAG_NO_EOI,    "NO_EOI"    },
 };

diff --git a/arch/powerpc/sysdev/xive/native.c b/arch/powerpc/sysdev/xive/native.c
index 6c04ac1f3a1fe2844a6db8fadc92103ec5923264..e91519c4246354baf6dcf98b6c8b02d31ac50347 100644 (file)
--- a/arch/powerpc/sysdev/xive/native.c
+++ b/arch/powerpc/sysdev/xive/native.c
@@ -64,8 +64,6 @@ int xive_native_populate_irq_data(u32 hw_irq, struct xive_irq_data *data)
                data->flags |= XIVE_IRQ_FLAG_STORE_EOI;
        if (opal_flags & OPAL_XIVE_IRQ_LSI)
                data->flags |= XIVE_IRQ_FLAG_LSI;
-       if (opal_flags & OPAL_XIVE_IRQ_EOI_VIA_FW)
-               data->flags |= XIVE_IRQ_FLAG_EOI_FW;
        data->eoi_page = be64_to_cpu(eoi_page);
        data->trig_page = be64_to_cpu(trig_page);
        data->esb_shift = be32_to_cpu(esb_shift);
@@ -380,15 +378,6 @@ static void xive_native_update_pending(struct xive_cpu *xc)
        }
 }
 
-static void xive_native_eoi(u32 hw_irq)
-{
-       /*
-        * Not normally used except if specific interrupts need
-        * a workaround on EOI.
-        */
-       opal_int_eoi(hw_irq);
-}
-
 static void xive_native_setup_cpu(unsigned int cpu, struct xive_cpu *xc)
 {
        s64 rc;
@@ -471,7 +460,6 @@ static const struct xive_ops xive_native_ops = {
        .match                  = xive_native_match,
        .shutdown               = xive_native_shutdown,
        .update_pending         = xive_native_update_pending,
-       .eoi                    = xive_native_eoi,
        .setup_cpu              = xive_native_setup_cpu,
        .teardown_cpu           = xive_native_teardown_cpu,
        .sync_source            = xive_native_sync_source,

diff --git a/arch/powerpc/sysdev/xive/spapr.c b/arch/powerpc/sysdev/xive/spapr.c
index 6610e5149d5aa0f723c1ff13c03deec79d6db37b..01ccc0786ada6cdd7551c4c514ffa4f3e93b2db6 100644 (file)
--- a/arch/powerpc/sysdev/xive/spapr.c
+++ b/arch/powerpc/sysdev/xive/spapr.c
@@ -628,11 +628,6 @@ static void xive_spapr_update_pending(struct xive_cpu *xc)
        }
 }
 
-static void xive_spapr_eoi(u32 hw_irq)
-{
-       /* Not used */;
-}
-
 static void xive_spapr_setup_cpu(unsigned int cpu, struct xive_cpu *xc)
 {
        /* Only some debug on the TIMA settings */
@@ -677,7 +672,6 @@ static const struct xive_ops xive_spapr_ops = {
        .match                  = xive_spapr_match,
        .shutdown               = xive_spapr_shutdown,
        .update_pending         = xive_spapr_update_pending,
-       .eoi                    = xive_spapr_eoi,
        .setup_cpu              = xive_spapr_setup_cpu,
        .teardown_cpu           = xive_spapr_teardown_cpu,
        .sync_source            = xive_spapr_sync_source,

diff --git a/arch/powerpc/sysdev/xive/xive-internal.h b/arch/powerpc/sysdev/xive/xive-internal.h
index c07fadb9d2644807db03c45bab08e24a06434a4b..9cf57c722faa3d1a0e1d3c29b1d203ea946ed504 100644 (file)
--- a/arch/powerpc/sysdev/xive/xive-internal.h
+++ b/arch/powerpc/sysdev/xive/xive-internal.h
@@ -52,7 +52,6 @@ struct xive_ops {
        void    (*shutdown)(void);
 
        void    (*update_pending)(struct xive_cpu *xc);
-       void    (*eoi)(u32 hw_irq);
        void    (*sync_source)(u32 hw_irq);
        u64     (*esb_rw)(u32 hw_irq, u32 offset, u64 data, bool write);
 #ifdef CONFIG_SMP