arm64: dts imx8mn: Remove non-existent USB OTG2

According to the i.MX8MN TRM, there is only one OTG port.  The
address for OTG2 is reserved on Nano.

This patch removes the non-existent OTG2, usbphynop2, and the usbmisc2
nodes.

Fixes: 6c3debcbae47 ("arm64: dts: freescale: Add i.MX8MN dtsi support")
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index 746faf1cf2fb7deecfbb1a22419bd831bbbcbb33..16c7202885d7094bdc03f0a07188a3a7e2d17c54 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -790,28 +790,6 @@
                                #index-cells = <1>;
                                reg = <0x32e40200 0x200>;
                        };
-
-                       usbotg2: usb@32e50000 {
-                               compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb";
-                               reg = <0x32e50000 0x200>;
-                               interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
-                               clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>;
-                               clock-names = "usb1_ctrl_root_clk";
-                               assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>,
-                                                 <&clk IMX8MN_CLK_USB_CORE_REF>;
-                               assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>,
-                                                        <&clk IMX8MN_SYS_PLL1_100M>;
-                               fsl,usbphy = <&usbphynop2>;
-                               fsl,usbmisc = <&usbmisc2 0>;
-                               status = "disabled";
-                       };
-
-                       usbmisc2: usbmisc@32e50200 {
-                               compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc";
-                               #index-cells = <1>;
-                               reg = <0x32e50200 0x200>;
-                       };
-
                };
 
                dma_apbh: dma-controller@33000000 {
@@ -876,12 +854,4 @@
                assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>;
                clock-names = "main_clk";
        };
-
-       usbphynop2: usbphynop2 {
-               compatible = "usb-nop-xceiv";
-               clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
-               assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
-               assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>;
-               clock-names = "main_clk";
-       };
 };